For best performance the common mode signals should

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Unformatted text preview: output coding. The proprietary 5-level architecture ensures minimum quantization noise at the outputs of the modulators without disturbing linearity or inducing additional distortion. The sampling frequency is DMCLK (typically 1 MHz with MCLK = 4 MHz) so the modulator outputs are refreshed at a DMCLK rate. The modulator outputs are available in the MOD register or serially transferred on each MDAT pin. Both modulators also include a dithering algorithm that can be enabled through the DITHER<1:0> bits in the Configuration register. This dithering process improves THD and SFDR (for high OSR settings) while slightly increasing the noise floor of the ADCs. For power metering applications and applications that are distortion-sensitive, it is recommended to keep DITHER enabled for both ADCs. In the case of power metering applications, THD and SFDR are critical specifications to optimize SNR (noise floor). This is not really problematic due to a large averaging factor at the output of the ADCs; therefore, even for low OSR settings, the dithering algorithm will show a positive impact on the performance of the application. Figure 5-1 represents a simplified block diagram of the Delta-Sigma ADC present on MCP3901. 5.2 Programmable Gain Amplifiers (PGA) The two Programmable Gain Amplifiers (PGAs) reside at the front end of each Delta-Sigma ADC. They have two functions: translate the common-mode of the input from AGND to an internal level between AGND and AVDD, and amplify the input differential signal. The translation of the common-mode does not change the differential signal, but recenters the common-mode so that the input signal can be properly amplified. The PGA block can be used to amplify very low signals, but the differential input range of the Delta-Sigma modulator must not be exceeded. The PGA is controlled by the PGA_CHn<2:0> bits in the GAIN register. The following table represents the gain settings for the PGA: Loop Filter Differential Voltage Input SecondOrder Integrator Quantizer Output 5-Level Flash ADC Bitstream TABLE 5-1: PGA CONFIGURATION SETTING Gain (V/V) 1 2 4 8 16 32 Gain (dB) 0 6 12 18 24 30 VIN Range (V) 0.5 0.25 0.125 0.0625 0.03125 0.015625 Gain PGA_CHn<2:0> 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 DAC MCP3901 Delta-Sigma Modulator FIGURE 5-1: Block Diagram. Simplified Delta-Sigma ADC 2011 Microchip Technology Inc. DS22192D-page 25 MCP3901 5.3.2 MODULATOR INPUT RANGE AND SATURATION POINT TABLE 5-2: Comp<3:0> Code 1111 0111 0011 0001 0000 DELTA-SIGMA MODULATOR CODING Modulator Output Code +2 +1 0 -1 -2 MDAT Serial Stream 1111 0111 0011 0001 0000 For a specified voltage reference value of 2.4V, the modulators' specified differential input range is 500 mV. The input range is proportional to VREF and scales according to the VREF voltage. This range ensures the stability of the modulator over amplitude and frequency. Outside of this range, the modulator is still functional, however, its stability is no longer ensured, and therefore, it is not recommended to exceed this limit. The saturation point for the modulator is VREF/3, since the transfer function of the ADC includes a gain of 3 by default (independent from the PGA setting). See Section 5.6 "ADC Output Coding". COMP COMP COMP COMP <0> <1> <3> <2> AMCLK DMCLK 5.3.3 BOOST MODE The Delta-Sigma modulators also include an independent BOOST mode for each channel. If the corresponding BOOST<1:0> bits are enabled, the power consumption of the modulator is multiplied by 2. Its bandwidth is increased to be able to sustain AMCLK clock frequencies up to 8.192 MHz, while keeping the ADC accuracy. When disabled, the power consumption is back to normal and the AMCLK clock frequencies can only reach up to 5 MHz without affecting ADC accuracy. MDAT+2 MDAT+1 MDAT+0 5.4 Modulator Output Block If the user wishes to use the modulator output of the device, the appropriate bits to enable the modulator output must be set in the Configuration register. When MODOUT<1:0> are enabled, the modulator output of the corresponding channel is present at the corresponding MDAT output pin as soon as the command is placed. Since the Delta-Sigma modulators have a 5-level output given by the state of 4 comparators with thermometer coding, their outputs can be represented on 4 bits. Each bit gives the state of the corresponding comparator (see Table 5-2). These bits are present on the MOD register and are updated at the DMCLK rate. In order to output the comparators result on a separate pin (MDAT0 and MDAT1), these comparator output bits have been arranged to be serially output at the AMCLK rate (see Figure 5-2). This 1-bit serial bitstream is the same as what would be produced by a 1-bit DAC modulator with a sampling frequency of AMCLK. The modulator can either be considered as a 5 level-output at DMCLK rate or a 1-bit output at AMCLK rate. These two representations are interchangeable. The MDAT outputs can, therefore, be used in any application that requires 1-bit modulator outputs. These applications w...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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