In these modes sck can idle either high or low each

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Unformatted text preview: DAT0/1 are also provided on separate pins for advanced communication. The MCP3901 interface has a simple command structure. The first byte transmitted is always the CONTROL byte and is followed by data bytes that are 8-bit wide. Both ADCs are continuously converting data by default and can be reset or shut down through a CONFIG2 register setting. Since each ADC data is either 16 or 24 bits (depending on the WIDTH bits), the internal registers can be grouped together with various configurations (through the READ bits) in order to allow easy data retrieval within only one communication. For device reads, the internal address counter can be automatically incremented in order to loop through groups of data within the register map. The SDO will then output the data located at the ADDRESS (A<4:0>) defined in the control byte and then ADDRESS + 1 depending on the READ<1:0> bits, which select the groups of registers. These groups are defined in Section 7.1 "ADC Channel Data Output Registers" (Register Map). The Data Ready pin (DR) can be used as an interrupt for an MCU and outputs pulses when new ADC channel data is available. The RESET pin acts like a Hard Reset and can reset the part to its default powerup configuration. The MDAT0/1 pins give the modulator outputs (see Section 5.4 "Modulator Output Block"). Device Address Bits Register Address Bits FIGURE 6-1: Control Byte. The default device address bits are `00'. Contact the Microchip factory for additional device address bits. For more information, please see the Product Identification System section. A read on undefined addresses will give an all zeros output on the first, and all subsequent transmitted bytes. A write on an undefined address will have no effect and also, will not increment the address counter. The register map is defined in Section 7.1 "ADC Channel Data Output Registers". 6.3 Reading from the Device The first data byte read is the one defined by the address given in the CONTROL byte. After this first byte is transmitted, if the CS pin is maintained low, the communication continues and the address of the next transmitted byte is determined by the status of the READ bits in the STATUS/COM register. Multiple looping configurations can be defined through the READ<1:0> bits for the address increment (see Section 6.6 "SPI MODE 0,0 Clock Idle Low, Read/ Write Examples"). 6.4 Writing to the Device 6.2 Control Byte The control byte of the MCP3901 contains two device Address bits, A<6:5>, 5 register Address bits, A<4:0>, and a Read/Write bit (R/W). The first byte transmitted to the MCP3901 is always the control byte. The MCP3901 interface is device addressable (through A<6:5>) so that multiple MCP3901 chips can be present on the same SPI bus with no data bus contention. This functionality enables three-phase power metering systems, containing three MCP3901 chips, controlled by a single SPI bus (single CS, SCK, SDI and SDO pins). The first data byte written is the one defined by the address given in the control byte. The write communication automatically increments the address for subsequent bytes. The address of the next transmitted byte within the same communication (CS stays low) is the next address defined on the register map. At the end of the register map, the address loops to the beginning of the register map. Writing a non-writable register has no effect. The SDO pin stays in high-impedance during a write communication. 6.5 SPI MODE 1,1 Clock Idle High, Read/Write Examples In this SPI mode, the clock Idles high. For the MCP3901, this means that there will be a falling edge before there is a rising edge. Note: Changing from an SPI Mode 1,1 to an SPI Mode 0,0 is possible, but needs a Reset pulse in-between to ensure correct communication. 2011 Microchip Technology Inc. DS22192D-page 33 MCP3901 : CS Data Transitions on the Falling Edge MCU and MCP3901 Latch Bits on the Rising Edge SCK SDI A6 A5 A4 A3 A2 A1 A0 R/W SDO HI-Z HI-Z D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 HI-Z (ADDRESS + 1) DATA (ADDRESS) DATA FIGURE 6-2: CS Device Read (SPI Mode 1,1 Clock Idles High). Data Transitions on the Falling Edge MCU and MCP3901 Latch Bits on the Rising Edge SCK SDI HI-Z A6 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 (ADDRESS) DATA HI-Z (ADDRESS + 1) DATA HI-Z SDO FIGURE 6-3: Device Write (SPI Mode 1,1 Clock Idles High). DS22192D-page 34 2011 Microchip Technology Inc. MCP3901 6.6 SPI MODE 0,0 Clock Idle Low, Read/Write Examples In this SPI mode, the clock Idles low. For the MCP3901, this means that there will be a rising edge before there is a falling edge. CS Data Transitions on the Falling Edge MCU and MCP3901 Latch Bits on the Rising Edge SCK SDI A6 A5 A4 A3 A2 A1 A0 R/W SDO HI-Z HI-Z D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 OF (ADDRESS + 2) DATA HI-Z (ADDRESS) DATA (ADDRESS + 1) DATA FIGURE 6-4: Device Read (SPI Mode 0,0 Clock Idles Low). CS Data Transitions on the Falling Edge MCU and MCP3901 Latch Bits on the Rising Edge SCK SDI HI-Z A6 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 OF (ADDRESS + 2) DATA (ADDRESS) DATA HI-Z (ADDRESS + 1) DATA HI-Z SDO FIGURE 6-5: Device Write (SPI Mode 0,0 Clock Idles Low)....
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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