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Unformatted text preview: s are linked together. In this mode, the output of the two ADCs is latched synchronously at the moment of the DR event. This prevents bad synchronization between the two ADCs. The output is also latched at the beginning of a reading in order not to be updated during a read and not to give erroneous data. DS22192D-page 46 2011 Microchip Technology Inc. MCP3901
R/W-1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 STATUS AND COMMUNICATION REGISTER: ADDRESS 0x09
R/W-1 DR_LTY R/W-0 DR_HIZN R/W-0 R/W-0 R-1 R-1 bit 0 DRMODE<1> DRMODE<0> DRSTATUS_CH1 DRSTATUS_CH0 READ<1> READ<0> READ<1:0>: Address Loop Setting bits 11 = Address counter loops on entire register map 10 = Address counter loops on register types (default) 01 = Address counter loops on register groups 00 = Address not incremented, continually read same single register DR_LTY: Data Ready Latency Control bit 1 = "No Latency" Conversion, DR pulses after 3 DRCLK periods (default) 0 = Unsettled Data is available after every DRCLK period DR_HIZN: Data Ready Pin Inactive State Control bit 1 = The data ready pin default state is a logic high when data is NOT ready 0 = The data ready pin default state is high-impedance when data is NOT ready (default) DRMODE<1:0>: Data Ready Pin (DR) Control bits 11 = Both Data Ready pulses from ADC0 and ADC Channel 1 are output on the DR pin. 10 = Data Ready pulses from ADC Channel 1 are output on the DR pin. DR from ADC Channel 0 are not present on the pin. 01 = Data Ready pulses from ADC Channel 0 are output on the DR pin. DR from ADC Channel 1 are not present on the pin. 00 = Data Ready pulses from the lagging ADC between the two are output on the DR pin. The lagging ADC selection depends on the PHASE register and on the OSR (default). DRSTATUS_CH<1:0>: Data Ready Status bits 11 = ADC Channel 1 and Channel 0 data is not ready (default) 10 = ADC Channel 1 data is not ready, ADC Channel 0 data is ready 01 = ADC Channel 0 data is not ready, ADC Channel 1 data is ready 00 = ADC Channel 1 and Channel 0 data is ready bit 5 bit 4 bit 3-2 bit 1-0 2011 Microchip Technology Inc. DS22192D-page 47 MCP3901
7.6 Configuration Registers
The Configuration registers contain settings for the internal clock prescaler, the oversampling ratio, the Channel 0 and Channel 1 width settings of 16 or 24 bits, the modulator output control settings, the state of the channel Resets and shutdowns, the dithering algorithm control (for Idle tones suppression), and the control bits for the external VREF and external CLK. REGISTER 7-6:
R/W-0 PRESCALE <1> bit 15 R/W-0 RESET _CH1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 CONFIGURATION REGISTERS: CONFIG1: ADDRESS 0x0A, CONFIG2: ADDRESS 0x0B
R/W-0 R/W-0 OSR<1> R/W-1 OSR<0> R/W-0 WIDTH _CH1 R/W-1 DITHER _CH1 R/W-0 WIDTH _CH0 R/W-1 DITHER _CH0 R/W-0 MODOUT _CH1 R/W-0 VREFEXT R/W-0 MODOUT _CH0 bit 8 R/W-0 RESET _CH0 R/W-0 SHUTDOWN _CH1 R/W-0 SHUTDOWN _CH0 R/W-0 CLKEXT bit 0 PRESCALE <0> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PRESCALE<1:0>: Internal Master Clock (AMCLK) Prescaler Value bits 11 = AMCLK = MCLK/8 10 = AMCLK = MCLK/4 01 = AMCLK = MCLK/2 00 = AMCLK = MCLK (default) OSR<1:0>: Oversampling Ratio for Delta-Sigma A/D Conversion bits (all channels, DMCLK/DRCLK) 11 = 256 10 = 128 01 = 64 (default) 00 = 32 WIDTH_CH<1:0>: ADC Channel Output Data Word Width bits 1 = 24-bit mode 0 = 16-bit mode (default) MODOUT_CH<1:0>: Modulator Output Setting for MDAT Pins bits 11 = Both CH0 and CH1 modulator outputs present on MDAT1 and MDAT0 pins 10 = CH1 ADC modulator output present on MDAT1 pin 01 = CH0 ADC modulator output present on MDAT0 pin 00 = No modulator output is enabled (default) RESET_CH<1:0>: Reset Mode Setting for ADCs bits 11 = Both CH0 and CH1 ADC are in Reset mode 10 = CH1 ADC in Reset mode 01 = CH0 ADC in Reset mode 00 = Neither Channel in Reset mode (default) SHUTDOWN_CH<1:0>: Shutdown Mode Setting for ADCs bits 11 = Both CH0 and CH1 ADC are in Shutdown 10 = CH1ADC is in shutdown 01 = CH0 ADC is in shutdown 00 = Neither Channel is in shutdown (default) DITHER_CH<1:0>: Control for Dithering Circuit bits 11 = Both CH0 and CH1 ADC have dithering circuit applied (default) 10 = Only CH1 ADC has dithering circuit applied 01 = Only CH0 ADC has dithering circuit applied 00 = Neither Channel has dithering circuit applied bit 13-12 bit 11-10 bit 9-8 bit 7-6 bit 5-4 bit 3-2 DS22192D-page 48 2011 Microchip Technology Inc. MCP3901
bit 1 CONFIGURATION REGISTERS: CONFIG1: ADDRESS 0x0A, CONFIG2: ADDRESS 0x0B (CONTINUED) VREFEXT: Internal Voltage Reference Shutdown Control bit 1 = Internal voltage reference disabled, an external voltage reference must be placed between REFIN+/OUT and REFIN0 = Internal voltage reference enabled (default) CLKEXT: Clock Mode bit 1 = External Clock mode (internal oscillator disabled and bypassed lower power)...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.
- Spring '13