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Unformatted text preview: DD) This pin is active low and places the entire chip in a Reset state when active. When RESET = 0, all registers are reset to their default value, no communication can take place and no clock is distributed inside the part. This state is equivalent to a POR state. Since the default state of the ADCs is on, the analog power consumption when RESET = 0 is equivalent to when RESET = 1. Only the digital power consumption is largely reduced because this current consumption is essentially dynamic and is reduced drastically when there is no clock running. All the analog biases are enabled during a Reset so that the part is fully operational just after a RESET rising edge. This input is Schmitt triggered. DVDD is the power supply pin for the digital circuitry within the MCP3901. This pin requires appropriate bypass capacitors and should be maintained between 2.7V and 5.5V for specified operation. 3.3 Analog VDD (AVDD) AVDD is the power supply pin for the analog circuitry within the MCP3901. This pin requires appropriate bypass capacitors and should be maintained to 5V 10% for specified operation. 2011 Microchip Technology Inc. DS22192D-page 15 MCP3901
3.4 ADC Differential Analog inputs (CHn+/CHn-) 3.7 Inverting Reference Input (REFIN-)
This pin is the inverting side of the differential voltage reference input for both ADCs. When using an external differential voltage reference, it should be connected to its VREF- pin. When using an external, single-ended voltage reference, or when VREFEXT = 0 (default) and using the internal voltage reference, this pin should be directly connected to AGND. CH0- and CH0+, and CH1- and CH1+, are the two fully differential analog voltage inputs for the Delta-Sigma ADCs. The linear and specified region of the channels are dependent on the PGA gain. This region corresponds to a differential voltage range of 500 mV/GAIN with VREF = 2.4V. The maximum absolute voltage, with respect to AGND, for each CHn+/- input pin is 1V with no distortion and 6V with no breaking after continuous voltage. 3.8 Digital Ground Connection (DGND) 3.5 Analog Ground (AGND) AGND is the ground connection to internal analog circuitry (ADCs, PGA, voltage reference, POR). To ensure accuracy and noise cancellation, this pin must be connected to the same ground as DGND, preferably with a star connection. If an analog ground plane is available, it is recommended that this pin be tied to this plane of the PCB. This plane should also reference all other analog circuitry in the system. DGND is the ground connection to internal digital circuitry (SINC filters, oscillator, serial interface). To ensure accuracy and noise cancellation, DGND must be connected to the same ground as AGND, preferably with a star connection. If a digital ground plane is available, it is recommended that this pin be tied to this plane of the Printed Circuit Board (PCB). This plane should also reference all other digital circuitry in the system. 3.9 Modulator Data Output Pin for Channel 1 and Channel 0 (MDAT1/MDAT0) 3.6 Non-Inverting Reference Input, Internal Reference Output (REFIN+/OUT) This pin is the non-inverting side of the differential voltage reference input for both ADCs or the internal voltage reference output. When VREFEXT = 1, and an external voltage reference source can be used, the internal voltage reference is disabled. When using an external differential voltage reference, it should be connected to its VREF+ pin. When using an external single-ended reference, it should be connected to this pin. When VREFEXT = 0, the internal voltage reference is enabled and connected to this pin through a switch. This voltage reference has minimal drive capability, and thus, needs proper buffering and bypass capacitances (10 F tantalum in parallel with 0.1 F ceramic) if used as a voltage source. For optimal performance, bypass capacitances should be connected between this pin and AGND at all times, even when the internal voltage reference is used. However, these capacitors are not mandatory to ensure proper operation. MDAT0 and MDAT1 are the output pins for the modulator serial bitstreams of ADC Channels 0 and 1, respectively. These pins are high-impedance by default. When the MODOUT<1:0> are enabled, the modulator bitstream of the corresponding channel is present on the pin and updated at the AMCLK frequency. (See Section 5.4 "Modulator Output Block" for a complete description of the modulator outputs.) These pins can be directly connected to a MCU or DSP when a specific digital filtering is needed. 3.10 DR (Data Ready Pin) The data ready pin indicates if a new conversion result is ready to be read. The default state of this pin is high when DR_HIZN = 1 and is high-impedance when DR_HIZN = 0 (default). After each conversion is finished, a low pulse will take place on the data ready pin to indicate the conversion result is ready as an interrupt. This pulse is synchronous with the master clock and has a defined and constant width. The data ready pin is independent of the SPI interface and acts like an interrupt output. The data ready pin state is not latched and the pulse...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.
- Spring '13