Osr 128 the delay can go from 64 to 63 phase6 is the

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Unformatted text preview: t; the LSB. OSR = 64: The delay can go from -32 to +31. PHASE<5> is the sign bit. Phase<4> is the MSB and PHASE<0> the LSB. OSR = 32: The delay can go from -16 to +15. PHASE<4> is the sign bit. Phase<3> is the MSB and PHASE<0> the LSB. EQUATION 7-1: Phase Register Code Delay = ------------------------------------------------DMCLK REGISTER 7-3: R/W-0 PHASE<7> bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 PHASE REGISTER (PHASE): ADDRESS 0x07 R/W-0 R/W-0 PHASE<5> R/W-0 PHASE<4> R/W-0 PHASE<3> R/W-0 PHASE<2> R/W-0 PHASE<1> R/W-0 PHASE<0> bit 0 PHASE<6> W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PHASE<7:0>: CH0 Relative to CH1 Phase Delay bits Delay = PHASE Register's two's complement code/DMCLK (Default PHASE = 0). DS22192D-page 44 2011 Microchip Technology Inc. MCP3901 7.4 Gain Configuration Register This register contains the settings for the PGA gains for each channel as well as the BOOST options for each channel. REGISTER 7-4: R/W-0 PGA_CH1 <2> bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 GAIN CONFIGURATION REGISTER (GAIN): ADDRESS 0x08 R/W-0 PGA_CH1 <1> R/W-0 PGA_CH1 <0> R/W-0 BOOST_ CH1 R/W-0 BOOST_ CH0 R/W-0 PGA_CH0 <2> R/W-0 PGA_CH0 <1> R/W-0 PGA_CH0 <0> bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PGA_CH1<2:0>: PGA Setting for Channel 1 bits 111 = Reserved (Gain = 1) 110 = Reserved (Gain = 1) 101 = Gain is 32 100 = Gain is 16 011 = Gain is 8 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1 BOOST_CH<1:0> Current Scaling for High-Speed Operation bits 11 = Both channels have current x 2 10 = Channel 1 has current x 2 01 = Channel 0 has current x 2 00 = Neither channel has current x 2 PGA_CH0<2:0>: PGA Setting for Channel 0 bits 111 = Reserved (Gain = 1) 110 = Reserved (Gain = 1) 101 = Gain is 32 100 = Gain is 16 011 = Gain is 8 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1 bit 4-3 bit 2-0 2011 Microchip Technology Inc. DS22192D-page 45 MCP3901 7.5 Status and Communication Register This mode is very useful for power metering applications because the data from both ADCs can be retrieved, using this single data ready event, and processed synchronously even in case of a large phase difference. This mode works as if there was one ADC channel and its data would be 48 bits long and contain both channel data. As a consequence, if one channel is in Reset or shutdown when DRMODE = 00, no data ready pulse will be present at the outputs (if both channels are not ready in this mode, the data is not considered ready). See Section 6.9 "Data Ready Pin (DR)" for more details about data ready pin behavior. This register contains all settings related to the communication, including data ready settings and status, and Read mode settings. 7.5.1 DATA READY (DR) LATENCY CONTROL DR_LTY This bit determines if the first data ready pulses correspond to settled data or unsettled data from each SINC3 filter. Unsettled data will provide DR pulses every DRCLK period. If this bit is set, unsettled data will wait for 3 DRCLK periods before giving DR pulses and will then give DR pulses every DRCLK period. 7.5.4 7.5.2 DATA READY (DR) PIN HIGH Z DR_HIZN DR STATUS FLAG DRSTATUS<1:0> This bit defines the non-active state of the data ready pin (logic 1 or high-impedance). Using this bit, the user can connect multiple chips with the same DR pin with a pull-up resistor (DR_HIZN = 0) or a single chip with no external component (DR_HIZN = 1). These bits indicate the DR status of both channels, respectively. These flags are set to logic high after each read of the STATUS/COM register. These bits are cleared when a DR event has happened on its respective ADC channel. Writing these bits has no effect. Note: These bits are useful if multiple devices share the same DR output pin (DR_HIZN = 0), in order to understand what DR event happened. This configuration can be used for three-phase power metering systems, where all three phases share the same data ready pin. In case the DRMODE = 00 (linked ADCs), these data ready status bits will be updated synchronously upon the same event (lagging ADC is ready). These bits are also useful in systems where the DR pin is not used to save MCU I/O. 7.5.3 DATA READY MODE DRMODE<1:0> If one of the channels is in Reset or shutdown, only one of the data ready pulses is present and the situation is similar to DRMODE = 01 or 10. In the `01', `10' and `11' modes, the ADC channel data to be read is latched at the beginning of a reading in order to prevent the case of erroneous data when a DR pulse happens during a read. In these modes, the two channels are independent. When these bits are equal to `11','10' or `01', they control which ADC's data ready is present on the DR pin. When DRMODE = 00, the data ready pin output is synchronized with the lagging ADC channel (defined by the PHASE register) and the ADC...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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