Temperature total harmonic distortion dbc 0 total

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Unformatted text preview: ortion Total Harmonic Distortion (dBc) 100 80 60 40 20 0 -20 -40 -60 -80 10 100 SINC filter notch at 15.625 Hz fD = 15.625 ksps 90 80 70 SINAD (dB) 60 50 40 30 20 10 0 10 100 fD = 15.625 ksps SINC filter notch at 15.625 Hz 1000 10000 1000 10000 Input Signal Frequency (Hz) Input Signal Frequency (Hz) FIGURE 2-15: Total Harmonic Distortion vs. Input Signal Frequency. FIGURE 2-18: Signal-to-Noise and Distortion vs. Input Frequency. 2011 Microchip Technology Inc. DS22192D-page 11 MCP3901 Note: Unless otherwise indicated, AVDD = 5.0V, DVDD = 5.0V; TA = +25C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS @ 60 Hz. 0.6 0.5 Offset Error (mV) 0.4 0.3 0.2 0.1 0 G=2 G=16 G=1 G=32 G=4 G=8 1 2 Frequency of Occurance 1 0 fIN = 60 Hz MCLK = 4 MHz OSR = 64 Dithering OFF 8 6 4 2 -0.1 -0.2 -0.3 -50 -25 0 25 50 75 Temperature (C) 0 78.9 79 79.1 79.2 79.3 79.4 79.5 79.6 79.7 79.8 SINAD (dB) 100 125 150 FIGURE 2-19: Signal-to-Noise and Distortion Histogram. 100 90 80 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 150 Temperature (C) FIGURE 2-22: Temperature. 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -50 Channel 0 Offset vs. Offset Error (mV) G=8 SINAD (dB) G=1 G=16 G=32 G=2 G=4 -25 0 25 50 75 100 125 150 Temperature (C) FIGURE 2-20: Signal-to-Noise and Distortion vs. Temperature. 100 FIGURE 2-23: Temperature. 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 -50 Channel 1 Offset vs. SINAD (dB) 60 40 20 0 -20 -40 0 - 20 - 40 - 60 - 80 Offset Error (mV) 80 Channel 0 Channel 1 -25 0 25 50 75 100 125 150 Input Amplitude (dBFS) Temperature (C) FIGURE 2-21: Signal-to-Noise and Distortion vs. Input Signal Amplitude. FIGURE 2-24: Channel-to-Channel Offset Match vs. Temperature. DS22192D-page 12 2011 Microchip Technology Inc. MCP3901 Note: Unless otherwise indicated, AVDD = 5.0V, DVDD = 5.0V; TA = +25C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS @ 60 Hz. 2.37165 2.3716 2.37155 2.3715 2.37145 2.3714 2.37135 2.3713 4.5 4.8 5.0 Power Supply (V) 5.3 5.5 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 -50 -25 0 25 50 75 100 Temperature (C) Positive Gain Error (% FS) G=1 G=2 G=8 G=16 G=4 G=32 125 150 FIGURE 2-25: Temperature. 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 -50 -25 0 Positive Gain Error vs. FIGURE 2-28: Internal Voltage Reference vs. Supply Voltage. 100 90 80 70 60 50 40 30 20 10 0 3 5 7 9 11 MCLK Frequency (MHz) Negative Gain Error (% FS) G=1 G=4 G=32 25 50 75 100 125 150 Temperature (C) FIGURE 2-26: Temperature 2.4 Int. Voltage Reference (V) Negative Gain Error vs. FIGURE 2-29: Signal-to-Noise and Distortion vs. Master Clock (MCLK), BOOST ON. SINAD (dB) G=2 G=8 G=16 Int. Voltage Reference (V) 8000 Frequency of Occurence 7000 6000 5000 4000 3000 2000 1000 2.39 2.38 2.37 2.36 2.35 -50 -25 0 25 50 75 100 Temperature (C) 125 150 Channel 0 VIN = 0V TA = +25C 16384 Consecutive Readings 24-bit Mode 0 -3000 -2000 -1000 0 1000 2000 3000 Output Code (LSB) FIGURE 2-27: vs. Temperature. Internal Voltage Reference FIGURE 2-30: Noise Histogram. 2011 Microchip Technology Inc. DS22192D-page 13 MCP3901 Note: Unless otherwise indicated, AVDD = 5.0V, DVDD = 5.0 V; TA = 25C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS @ 60 Hz. 100 80 60 40 20 0 -20 -40 -60 -80 -100 -0.5 OSR = 256 Dithering OFF SCK = 8 MHz 2.5 2 IDD (mA) 1.5 1 DIDD AIDD BOOST OFF INL (ppm) Channel 1 Channel 0 0.5 0 -0.25 0 Input Voltage (V) 0.25 0.5 0 1 2 3 MCLK (MHz) 4 5 6 FIGURE 2-31: (Dithering Off). 50 40 30 20 INL (ppm) 10 0 -10 -20 -30 -40 -50 -0.5 -0.25 Integral Nonlinearity FIGURE 2-33: Operating Current vs. Master Clock (MCLK). OSR = 256 Dithering ON SCK = 8 MHz Channel 0 Channel 1 0 0.25 Input Voltage (V) 0.5 FIGURE 2-32: (Dithering On). Integral Nonlinearity DS22192D-page 14 2011 Microchip Technology Inc. MCP3901 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Symbol PIN FUNCTION TABLE Pin No. Function SSOP QFN 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 21 Master Reset Logic Input Pin Digital Power Supply Pin Analog Power Supply Pin Non-Inverting Analog Input Pin for Channel 0 Inverting Analog Input Pin for Channel 0 Inverting Analog Input Pin for Channel 1 Non-Inverting Analog Input Pin for Channel 1 Analog Ground Pin, Return Path for Internal Analog Circuitry Non-Inverting Voltage Reference Input and Internal Reference Output Pin Inverting Voltage Reference Input Pin Digital Ground Pin, Return Path for Internal Digital Circuitry Modulator Data Output Pin for Channel 1 Modulator Data Output Pin for Channel 0 Data Ready Signal Output Pin Oscillator Crystal Connection Pin or External Clock Input Pin Oscillator Crystal Connection Pin Serial Interface Chip Select Pin Serial Interface Clock Pin Serial Interface Data Output Pin Serial Interface Data Input Pin Exposed Thermal Pad. Must be connected to AGND. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 -- RESET DVDD AVDD CH0+ CH0CH1CH1+ AGND REFIN+/OUT REFINDGND MDAT1 MDAT0 DR OSC1/CLKI OSC2 CS SCK SDO SDI EP 3.1 RESET 3.2 Digital VDD (DV...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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