The comparators output is 0011 for each adc the sinc

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Unformatted text preview: -impedance, and no clock is propagated through the chip. 5.10 Phase Delay Block The MCP3901 incorporates a phase delay generator which ensures that the two ADCs are converting the inputs with a fixed delay between them. The two ADCs are synchronously sampling but the averaging of modulator outputs is delayed. Therefore, the SINC filter outputs (thus, the ADC outputs) show a fixed phase delay, as determined by the PHASE register setting. The PHASE register (PHASE<7:0>) is a 7 bit + sign, MSB first, two's complement register that indicates how much phase delay there is to be between Channel 0 and Channel 1. The reference channel for the delay is Channel 1 (typically the voltage channel for power metering applications). When PHASE<7:0> are positive, Channel 0 is lagging versus Channel 1. When PHASE<7:0> are negative, Channel 0 is leading versus Channel 1. The amount of delay between two ADC conversions is given by the following formula: AVDD 5V 4.2V 4V 50 s tPOR 0V Device Mode Time Reset Proper Operation Reset EQUATION 5-5: Phase Register Code Delay = ------------------------------------------------DMCLK The timing resolution of the phase delay is 1/DMCLK or 1 s in the default configuration with MCLK = 4 MHz. The data ready signals are affected by the phase delay settings. Typically, the time difference between the data ready pulses of Channel 0 and Channel 1 is equal to the phase delay setting. Note: A detailed explanation of the Data Ready pin (DR) with phase delay is present in Section 6.10 "Data Ready Latches and Data Ready Modes (DRMODE<1:0>)". FIGURE 5-4: Power-on Reset Operation. DS22192D-page 30 2011 Microchip Technology Inc. MCP3901 5.10.1 PHASE DELAY LIMITS 5.11 Crystal Oscillator The phase delay can only go from -OSR/2 to +OSR/2 1. This sets the fine phase resolution. The PHASE register is coded with two's complement. If larger delays between the two channels are needed, they can be implemented externally to the chip with an MCU. A FIFO in the MCU can save incoming data from the leading channel for a number N of DRCLK clocks. In this case, DRCLK would represent the coarse timing resolution, and DMCLK, the fine timing resolution. The total delay will then be equal to: Delay = N/DRCLK + PHASE/DMCLK The Phase Delay register can be programmed once with the OSR = 256 setting and will adjust to the OSR automatically afterwards, without the need to change the value of the PHASE register. OSR = 256: The delay can go from -128 to +127. PHASE<7> is the sign bit, PHASE<6> is the MSB and PHASE<0> is the LSB. OSR = 128: The delay can go from -64 to +63. PHASE<6> is the sign bit, PHASE<5> is the MSB and PHASE<0> is the LSB. OSR = 64: The delay can go from -32 to +31. PHASE<5> is the sign bit, PHASE<4> is the MSB and PHASE<0> is the LSB. OSR = 32: The delay can go from -16 to +15. PHASE<4> is the sign bit, PHASE<3> is the MSB and PHASE<0> is the LSB. The MCP3901 includes a Pierce-type crystal oscillator with very high stability and ensures very low temperature and jitter for the clock generation. This oscillator can handle up to 16.384 MHz crystal frequencies provided that proper load capacitances and the quartz quality factor are used. For keeping specified ADC accuracy, AMCLK should be kept between 1 and 5 MHz with BOOST off or 1 and 8.192 MHz with BOOST on. Larger MCLK frequencies can be used provided the prescaler clock settings allow the AMCLK to respect these ranges. For a proper start-up, the load capacitors of the crystal should be connected between OSC1 and DGND, and between OSC2 and DGND. They should also respect the following equation: EQUATION 5-6: 2 6 1 R M < 1.6 10 ------------------------ f C LOAD Where: f CLOAD RM = = = Crystal frequency in MHz Load capacitance in pF including parasitics from the PCB Motional resistance in ohms of the quartz TABLE 5-8: PHASE VALUES WITH MCLK = 4 MHZ, OSR = 256 Hex Delay (CH0 relative to CH1) +127 s +126 s +1 s 0 s -1 s -127 s -128 s When CLKEXT = 1, the crystal oscillator is bypassed by a digital buffer to allow direct clock input for an external clock (see Figure 1-5). PHASE Register Value 01111111 01111110 00000001 00000000 11111111 10000001 10000000 0x7F 0x7E 0x01 0x00 0xFF 0x81 0x80 2011 Microchip Technology Inc. DS22192D-page 31 MCP3901 NOTES: DS22192D-page 32 2011 Microchip Technology Inc. MCP3901 6.0 6.1 SERIAL INTERFACE DESCRIPTION Overview A6 A5 A4 A3 A2 A1 A0 R/W Read/ Write Bit The MCP3901 device is compatible with SPI Modes 0,0 and 1,1. Data is clocked out of the MCP3901 on the falling edge of SCK and data is clocked into the MCP3901 on the rising edge of SCK. In these modes, SCK can Idle either high or low. Each SPI communication starts with a CS falling edge and stops with the CS rising edge. Each SPI communication is independent. When CS is high, SDO is in high-impedance, and transitions on SCK and SDI have no effect. Additional controls: RESET, DR and M...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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