The modulator can either be considered as a 5 level

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Unformatted text preview: ill often integrate and filter the 1-bit output with SINC or more complex decimation filters computed by an MCU or a DSP. MDAT-1 MDAT-2 FIGURE 5-2: MDAT Serial Outputs in Function of the Modulator Output Code. Since the Reset and shutdown SPI commands are asynchronous, the MDAT pins are resynchronized with DMCLK after each time the part goes out of Reset and shutdown. This means that the first output of MDAT after Reset is always `0011' after the first DMCLK rising edge. DS22192D-page 26 2011 Microchip Technology Inc. MCP3901 5.5 SINC3 Filter Both ADCs present in the MCP3901 include a decimation filter that is a third-order sinc (or notch) filter. This filter processes the multi-bit bitstream into 16 or 24-bit words (depending on the WIDTH Configuration bit). The settling time of the filter is 3 DMCLK periods. It is recommended that unsettled data be discarded to avoid data corruption, which can be done easily by setting the DR_LTY bit high in the STATUS/COM register. The resolution achievable at the output of the sinc filter (the output of the ADC) is dependant on the OSR and is summarized with the following table: The Normal Mode Rejection Ratio (NMRR) or gain of the transfer function is given by the following equation: EQUATION 5-2: MAGNITUDE OF FREQUENCY RESPONSE H(f) 3 f sin c --------------------- DMCLK NMRR ( f ) = --------------------------------------------f sin c -------------------- DRCLK or: f sin c --- fS NMRR ( f ) = ---------------------------f - sin c ---- fD where: sin ( x ) sin c ( x ) = -------------x 3 TABLE 5-3: OSR<1:0> 0 0 1 1 0 1 0 1 ADC RESOLUTION vs. OSR OSR 32 64 128 256 ADC Resolution (bits) No Missing Codes 17 20 23 24 For 24-Bit Output mode (WIDTH = 1), the output of the sinc filter is padded with least significant zeros for any resolution less than 24 bits. For 16-Bit Output modes, the output of the sinc filter is rounded to the closest 16-bit number in order to conserve only 16-bit words and to minimize truncation error. The gain of the transfer function of this filter is 1 at each multiple of DMCLK (typically 1 MHz) so a proper anti-aliasing filter must be placed at the inputs. This will attenuate the frequency content around DMCLK and keep the desired accuracy over the baseband of the converter. This anti-aliasing filter can be a simple, first-order RC network with a sufficiently low time constant to generate high rejection at DMCLK frequency. Figure 5-3 shows the sinc filter frequency response: 20 0 Magnitude (dB) -20 -40 -60 -80 -100 -120 1 10 100 1000 10000 100000 1000000 Input Frequency (Hz) EQUATION 5-1: SINC FILTER TRANSFER FUNCTION H(Z) 3 FIGURE 5-3: SINC Filter Response with MCLK = 4 MHz, OSR = 64, PRESCALE = 1. 1 z OSR H ( z ) = -------------------------------- OSR ( 1 z 1 ) Where: 2fj z = exp --------------------- DMCLK 2011 Microchip Technology Inc. DS22192D-page 27 MCP3901 5.6 ADC Output Coding The second-order modulator, SINC3 filter, PGA, VREF and analog input structure all work together to produce the device transfer function for the Analog-to-Digital conversion (see Equation 5-3). The channel data is either a 16-bit or 24-bit word, presented in a 23-bit or 15-bit plus sign, two's complement format, and is MSB (left) justified. The ADC data is two or three bytes wide depending on the WIDTH bit of the associated channel. The 16-bit mode includes a round to the closest 16-bit word (instead of truncation) in order to improve the accuracy of the ADC data. In case of positive saturation (CHn+ CHn- > VREF/3), the output is locked to 7FFFFF for 24-bit mode (7FFF for 16-bit mode). In case of negative saturation (CHn+ CHn- < -VREF/3), the output code is locked to 800000 for 24-bit mode (8000 for 16-bit mode). Equation 5-3 is only true for DC inputs. For AC inputs, this transfer function needs to be multiplied by the transfer function of the SINC3 filter (see Equation 5-1 and Equation 5-2). EQUATION 5-3: ( CH n+ CH n- ) DATA_CHn = ------------------------------------ 8,388,608 G 3 V REF+ V REF-- ( CH n+ CH n- ) DATA_CHn = ------------------------------------ 32, 768 G 3 V REF+ V REF-- 5.6.1 ADC RESOLUTION AS A FUNCTION OF OSR (For 24-Bit Mode or WIDTH = 1) (For 16-Bit Mode or WIDTH = 0) The ADC resolution is a function of the OSR (Section 5.5 "SINC3 Filter"). The resolution is the same for both channels. No matter what the resolution is, the ADC output data is always presented in 24-bit words, with added zeros at the end if the OSR is not large enough to produce 24-bit resolution (left justification). TABLE 5-4: 0 1 1 1 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 OSR = 256 OUTPUT CODE EXAMPLES ADC Output Code (MSB First) 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 Hexadecimal 0x7FFFFF 0x7FFFFE 0x000000 0xFFFFFF 0x800001 0x800000 Decimal + 8,388,607 + 8,388,606 0 -1 - 8,388,607 - 8,388,608 TABLE 5-5: OSR = 128 OUTPUT CODE EXAMPLES ADC Output Code (MSB First) Hexadecimal 1 1 1 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0x7FFFFE 0x7FFFFC 0x000000 0xFFFFFE 0x800002 0x800000 Decimal 23-Bit Resolution + 4,194,303 + 4,194,302 0 -1 - 4,194,303 - 4,194,304 0 1 1 1 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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