This error is filtered by the feedback loop and

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Unformatted text preview: tonal behavior, and thus, improving SFDR and THD (see Figure 2-10 and Figure 2-14). The dithering process scrambles the Idle tones into baseband white noise and ensures that dynamic specs (SNR, SINAD, THD, SFDR) are less signal dependent. The MCP3901 incorporates a proprietary dithering algorithm on both ADCs in order to remove Idle tones and improve THD, which is crucial for power metering applications. DS22192D-page 22 2011 Microchip Technology Inc. MCP3901 4.16 Crosstalk It is defined as: The crosstalk is defined as the perturbation caused by one ADC channel on the other ADC channel. It is a measurement of the isolation between the two ADCs present in the chip. This measurement is a two-step procedure: 1. 2. Measure one ADC input with no perturbation on the other ADC (ADC inputs shorted). Measure the same ADC input with a perturbation sine wave signal on the other ADC at a certain predefined frequency. Where VOUT is the equivalent input voltage that the output code translates to with the ADC transfer function. In the MCP3901 specification, AVDD varies from 4.5V to 5.5V, and for AC PSRR, a 50/60 Hz sinewave is chosen, centered around 5V with a maximum 500 mV amplitude. The PSRR specification is measured with AVDD = DVDD. EQUATION 4-11: V OUT PSRR ( dB ) = 20 log ------------------ AVDD The crosstalk is then the ratio between the output power of the ADC when the perturbation is present and when it is not divided by the power of the perturbation signal. A lower crosstalk value implies more independence and isolation between the two channels. The measurement of this signal is performed under the following conditions: GAIN = 1, PRESCALE = 1, OSR = 256, MCLK = 4 MHz 4.18 CMRR This is the ratio between a change in the common-mode input voltage and the ADC output codes. It measures the influence of the common-mode input voltage on the ADC outputs. The CMRR specification can be DC (the common-mode input voltage is taking multiple DC values) or AC (the common-mode input voltage is a sinewave at a certain frequency with a certain common-mode). In AC, the amplitude of the sinewave is representing the change in the power supply. It is defined as: Step 1 CH0+ = CH0- = AGND CH1+ = CH1- = AGND EQUATION 4-12: VOUT CMRR ( dB ) = 20 log ----------------- VCM Where VCM = (CHn+ + CHn-)/2 is the common-mode input voltage and VOUT is the equivalent input voltage, the output code is translated to the ADC transfer function. In the MCP3901 specification, VCM varies from -1V to +1V, and for the AC specification, a 50/ 60 Hz sinewave is chosen, centered around 0V, with a 500 mV amplitude. Step 2 CH0+ = CH0- = AGND CH1+ CH1- = 1 VP-P @ 50/60 Hz (full-scale sine wave) The crosstalk is then calculated with the following formula: EQUATION 4-10: CH0Power CTalk ( dB ) = 10 log -------------------------------- CH1Power 4.19 ADC Reset Mode 4.17 PSRR This is the ratio between a change in the power supply voltage and the ADC output codes. It measures the influence of the power supply voltage on the ADC outputs. The PSRR specification can be DC (the power supply is taking multiple DC values) or AC (the power supply is a sinewave at a certain frequency with a certain common-mode). In AC, the amplitude of the sinewave is representing the change in the power supply. ADC Reset mode (also called Soft Reset mode) can only be entered through setting the RESET<1:0> bits high in the Configuration register. This mode is defined as the condition where the converters are active, but their output is forced to `0'. The registers are not affected in this Reset mode and retain their values. The ADCs can immediately output meaningful codes after leaving Reset mode (and after the sinc filter settling time of 3/DRCLK). This mode is both entered and exited through the setting of bits in the Configuration register. 2011 Microchip Technology Inc. DS22192D-page 23 MCP3901 Each converter can be placed in Soft Reset mode independently. The Configuration registers are not modified by the Soft Reset mode. A data ready pulse will not be generated by any ADC while in Reset mode. Reset mode also effects the modulator output block (i.e., the MDAT pin, corresponding to the channel in Reset). If enabled, it provides a bitstream corresponding to a zero output (a series of `0011' bits continuously repeated). When an ADC exits ADC Reset mode, any phase delay present, before Reset was entered, will still be present. If one ADC was not in Reset, the ADC leaving Reset mode will automatically resynchronize the phase delay. The resynchronization is relative to the other ADC channel per the Phase Delay register block and gives DR pulses accordingly. If an ADC is placed in Reset mode while the other is converting, it is not shutting down the internal clock. When going back out of Reset, it will be resynchronized automatically with the clock that did not stop during Reset. If both ADCs are in Soft Reset or Shutdown modes, the clock is no longer distributed to the digital core for lowpower operation. Once any of the ADC is back to normal operation, the clock is automatically distri...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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