This pulse is synchronous with the master clock and

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: width (and period) are both determined by the MCLK frequency, over-sampling rate and internal clock prescale settings. The DR pulse width is equal to one DMCLK period and the frequency of the pulses is equal to DRCLK (see Figure 1-3). Note: This pin should not be left floating when the DR_HIZN bit is low; a 100 k pull-up is resistor connected to DVDD recommended. DS22192D-page 16 2011 Microchip Technology Inc. MCP3901 3.11 Oscillator and Master Clock Input Pins (OSC1/CLKI, OSC2) 3.14 SDO (Serial Data Output) This is the SPI data output pin. Data is clocked out of the device on the falling edge of SCK. This pin stays high-impedance during the first command byte. It also stays high-impedance during the whole communication for write commands, and when the CS pin is high or when the RESET pin is low. This pin is active only when a read command is processed. Each read is processed by a packet of 8 bits. OSC1/CLKI and OSC2 provide the master clock for the device. When CLKEXT = 0 (default), a resonant crystal or clock source with a similar sinusoidal waveform must be placed across these pins to ensure proper operation. The typical clock frequency specified is 4 MHz. However, the clock frequency can be 1 MHz to 5 MHz without disturbing ADC accuracy. With the current boost circuit enabled, the master clock can be used up to 8.192 MHz without disturbing ADC accuracy. Appropriate load capacitance should be connected to these pins for proper operation. Note: When CLKEXT = 1, the crystal oscillator is disabled, as well as the OSC2 input. The OSC1 becomes the master clock input, CLKI, the direct path for an external clock source; for example, a clock source generated by an MCU. 3.15 SDI (Serial Data Input) This is the SPI data input pin. Data is clocked into the device on the rising edge of SCK. When CS is low, this pin is used to communicate with a series of 8-bit commands. The interface is half-duplex (inputs and outputs do not happen at the same time). Each communication starts with a chip select falling edge, followed by an 8-bit command word entered through the SDI pin. Each command is either a read or a write command. Toggling SDI during a read command has no effect. This input is Schmitt triggered. 3.12 CS (Chip Select) This pin is the SPI chip select that enables the serial communication. When this pin is high, no communication can take place. A chip select falling edge initiates the serial communication and a chip select rising edge terminates the communication. No communication can take place, even when CS is low and when RESET is low. This input is Schmitt triggered. 3.13 SCK (Serial Data Clock) This is the serial clock pin for SPI communication. Data is clocked into the device on the rising edge of SCK. Data is clocked out of the device on the falling edge of SCK. The MCP3901 interface is compatible with both SPI 0,0 and 1,1 modes. SPI modes can only be changed during a Reset. The maximum clock speed specified is 20 MHz when DVDD > 4.5V and 10 MHz otherwise. This input is Schmitt triggered. 2011 Microchip Technology Inc. DS22192D-page 17 MCP3901 NOTES: DS22192D-page 18 2011 Microchip Technology Inc. MCP3901 4.0 TERMINOLOGY AND FORMULAS 4.2 AMCLK Analog Master Clock This is the clock frequency that is present on the analog portion of the device, after prescaling has occurred via the CONFIG1 PRESCALE<1:0> register bits. The analog portion includes the PGAs and the two Sigma-Delta modulators. This section defines the terms and formulas used throughout this data sheet. The following terms are defined: MCLK Master Clock AMCLK Analog Master Clock DMCLK Digital Master Clock DRCLK Data Rate Clock Oversampling Ratio (OSR) Offset Error Gain Error Integral Nonlinearity Error Signal-to-Noise Ratio (SNR) Signal-to-Noise Ratio And Distortion (SINAD) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) MCP3901 Delta-Sigma Architecture Idle Tones Dithering Crosstalk PSRR CMRR ADC Reset Mode Hardware Reset Mode (RESET = 0) ADC Shutdown Mode Full Shutdown Mode EQUATION 4-1: MCLK AMCLK = -----------------------------PRESCALE TABLE 4-1: Config PRE<1:0> 0 0 1 1 0 1 0 1 MCP3901 OVERSAMPLING RATIO SETTINGS Analog Master Clock Prescale AMCLK = MCLK/1 (default) AMCLK = MCLK/2 AMCLK = MCLK/4 AMCLK = MCLK/8 4.3 DMCLK Digital Master Clock This is the clock frequency that is present on the digital portion of the device, after prescaling and division by 4. This is also the sampling frequency, which is the rate when the modulator outputs are refreshed. Each period of this clock corresponds to one sample and one modulator output (see Figure 1-5). EQUATION 4-2: AMCLK MCLK DMCLK = -------------------- = --------------------------------------4 4 PRESCALE 4.1 MCLK Master Clock 4.4 This is the fastest clock present in the device. This is the frequency of the crystal placed at the OSC1/OSC2 inputs when CLKEXT = 0 or the frequency of the clock input at the OSC1/CLKI when CLKEXT = 1 (see Figure 1-5). DRCLK Data Rate Clock This is the...
View Full Document

This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

Ask a homework question - tutors are online