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Unformatted text preview: buted again. Each converter can be placed in Shutdown mode, independently. The CONFIG registers are not modified by the Shutdown mode. This mode is only available through programming the SHUTDOWN<1:0> bits in the CONFIG2 register. The output data is flushed to all zeros while in ADC shutdown. No data ready pulses are generated by any ADC while in ADC Shutdown mode. ADC Shutdown mode also effects the modulator output block (i.e., if MDAT of the channel in Shutdown mode is enabled). This pin will provide a bitstream corresponding to a zero output (series of `0011' bits continuously repeated). When an ADC exits ADC Shutdown mode, any phase delay present before shutdown was entered will still be present. If one ADC was not in shutdown, the ADC leaving Shutdown mode will automatically resynchronize the phase delay relative to the other ADC channel, per the Phase Delay register block, and give DR pulses accordingly. If an ADC is placed in Shutdown mode while the other is converting, it is not shutting down the internal clock. When going back out of shutdown, it will be resynchronized automatically with the clock that did not stop during Reset. If both ADCs are in ADC Reset or ADC Shutdown modes, there is no more distribution of the clock to the digital core for low-power operation. Once any of the ADC is back to normal operation, the clock is automatically distributed again. 4.20 Hard Reset Mode (RESET = 0) This mode is only available during a Power-on-Reset (POR) or when the RESET pin is pulled low. The RESET pin low state places the device in a Hard Reset mode. In this mode, all internal registers are reset to their default state. The DC biases for the analog blocks are still active (i.e., the MCP3901 is ready to convert). However, this pin clears all conversion data in the ADCs. In this mode, the MDAT outputs are in high-impedance. The comparator outputs of both ADCs are forced to their Reset state (`0011'). The SINC filters are all reset, as well as their double output buffers. See serial timing for minimum pulse low time in Section 1.0 "Electrical Characteristics". During a Hard Reset, no communication with the part is possible. The digital interface is maintained in a Reset state. 4.22 Full Shutdown Mode The lowest power consumption can be achieved when SHUTDOWN<1:0> = 11 and VREFEXT = CLKEXT = 1. This mode is called "Full Shutdown mode" and no analog circuitry is enabled. In this mode, the POR AVDD monitoring circuit is also disabled. When the clock is Idle (CLKI = 0 or 1 continuously), no clock is propagated throughout the chip. Both ADCs are in shutdown, the internal voltage reference is disabled and the internal oscillator is disabled. The only circuit that remains active is the SPI interface, but this circuit does not induce any static power consumption. If SCK is Idle, the only current consumption comes from the leakage currents induced by the transistors and is less than 1 A on each power supply. This mode can be used to power down the chip completely and avoid power consumption when there is no data to convert at the analog inputs. Any SCK or MCLK edge coming while on this mode, will induce dynamic power consumption. Once any of the SHUTDOWN, CLKEXT and VREFEXT bits returns to `0', the POR AVDD monitoring block is back to operation and AVDD monitoring can take place. 4.21 ADC Shutdown Mode ADC Shutdown mode is defined as a state where the converters and their biases are off, consuming only leakage current. After this is removed, start-up delay time (SINC filter settling time) will occur before outputting meaningful codes. The start-up delay is needed to power-up all DC biases in the channel that was in shutdown. This delay is the same as tPOR and any DR pulse coming within this delay should be discarded. DS22192D-page 24 2011 Microchip Technology Inc. MCP3901
5.1 DEVICE OVERVIEW
Analog Inputs (CHn+/-) 5.3
5.3.1 Delta-Sigma Modulator
ARCHITECTURE The MCP3901 analog inputs can be connected directly to current and voltage transducers (such as shunts, current transformers, or Rogowski coils). Each input pin is protected by specialized ESD structures that are certified to pass 7 kV HBM and 400V MM contact charge. These structures allow bipolar 6V continuous voltage, with respect to AGND, to be present at their inputs without the risk of permanent damage. Both channels have fully differential voltage inputs for better noise performance. The absolute voltage at each pin, relative to AGND, should be maintained in the 1V range during operation in order to ensure the specified ADC accuracy. The common-mode signals should be adapted to respect both the previous conditions and the differential input voltage range. For best performance, the common-mode signals should be maintained to AGND. Both ADCs are identical in the MCP3901 and they include a second-order modulator with a multi-bit DAC architecture (see Figure 5-1). The quantizer is a Flash ADC composed of 4 comparators with equally spaced thresholds and a thermometer...
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- Spring '13