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Unformatted text preview: SPI clock If 0 data is clocked out on the falling edge of the SPI clock If 1 the 'idle' clock line state is high. If 0 the 'idle' clock line state is low. R/W 0 7 6 Invert SPI CLK Shift out MS bit first R/W 0 If 1 the data is shifted out starting with the MS bit. R/W 0 (bit 15 or bit 11) If 0 the data is shifted out starting with the LS bit. (bit 0) Specifies the number of bits to shift R/W 0 This field is ignored when using 'variable shift' mode 5:0 Shift length Invert SPI CLK Changing this bit will immediately change the polarity of the SPI clock output. It is recommended not to do this when also the CS is active as the connected devices will see this as a clock change. DOUT hold time Because the interface runs of fast silicon the MOSI hold time against the clock will be very short. This can cause considerable problems on SPI slaves. To make it easier for the slave to see the data the hold time of the MOSI out against the SPI clock out is programmable.
CLK CLK MOSI No hold time MOSI With hold time Variable width In this mode the shift length is taken from the transmit FIFO. The transmit data bits 28:24 are used as shift length and the data bits 23:0 are the actual transmit data. If the option 'shift MS out first' is selected the first bit shifted out will be bit 23. The receive data will arrive as normal. Variable CS This mode is used together with the variable width mode. In this mode the CS pattern is taken from the transmit FIFO. The transmit data bits 31:29 are used as CS and the data bits 23:0 are the actual transmit data. This allows the CPU to write to different SPI devices without having to change the CS bits. However the data length is limited to 24 bits. Post-input mode Some rare SPI devices output data on the falling clock edge which then has to be picked up on the next falling clock edge. There are two problems with this: 1. The very first falling clock edge there is no valid data arriving. 2. After the last clock edge there is one more 'dangling' bit to pick up.
06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 23 The post-input mode is specifically to deal with this sort of data. If the post-input mode bit is set, the data arriving at the first falling clock edge is ignored. Then after the last falling clock edge the CS remain asserted and after a full bit time the last data bit is picked up. The following figure shows this behaviour:
Get first bit Clk Cs_n Get last bit In this mode the CS will go high 1 full SPI clock cycle after the last clock edge. This guarantees a full SPI clock cycle time for the data to settle and arrive at the MISO input. AUXSPI0/1_CNTL1 Register (0x7E21 5084,0x7E21 50C4)
SYNOPSIS The AUXSPIx_CNTL1 registers control more features of the SPI interfaces. Bit(s) Field Name 31:18 10:8 CS high time 7 6 5:2 1 Description Reserved, write zero, read as don't care Additional SPI clock cycles where the CS is high. Type Reset R/W 0 R/W 0 TX empty IRQ If 1 the interrupt line is high when the transmit FIFO is empty Done IRQ - If 1 the interrupt line is high when the interface is idle R/W 0 Reserved, write zero, read as don't care Shift in MS bit If 1 the data is shifted in starting with the MS bit. (bit R/W 0 first 15) If 0 the data is shifted in starting with the LS bit. (bit 0) Keep input If 1 the receiver shift register is NOT cleared. Thus new data is concatenated to old data. If 0 the receiver shift register is cleared before each transaction. R/W 0 0 Keep input Setting the 'Keep input' bit will make that the input shift register is not cleared between transactions. However the contents of the shift register is still written to the receive FIFO at the end of each transaction. E.g. if you receive two 8 bit values 0x81 followed by 0x46 the receive FIFO will contain: 0x0081 in the first entry and 0x8146 in the second entry. This mode may save CPU time concatenating bits (4 bits followed by 12 bits). 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 24 CS high time The SPI CS will always be high for at least 1 SPI clock cycle. Some SPI devices need more time to process the data. This field will set a longer CS-high time. So the actual CS high time is (CS_high_time + 1) (In SPI clock cycles). Interrupts The SPI block has two interrupts: TX FIFO is empty, SPI is Idle. TX FIFO is empty: This interrupt will be asserted as soon as the last entry has been read from the transmit FIFO. At that time the interface will still be busy shifting out that data. This also implies that the receive FIFO will not yet contain the last received data. It is possible at that time to fill the TX FIFO again and read the receive FIFO entries which have been received. There is a RX FIFO level field which tells exactly how many words are in the receive FIFO. In general at that time the receive FIFO should contain the number of Tx items minus o...
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- Spring '13