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Unformatted text preview: Select 00 = Chip select 0 01 = Chip select 1 10 = Chip select 2 11 = Reserved RW 0x0 7 TA RW 0x0 6 CSPOL RW 0x0 5:4 CLEAR RW 0x0 3 CPOL RW 0x0 2 CPHA RW 0x0 1:0 CS RW 0x0 FIFO Register
Synopsis This register allows TX data to be written to the TX FIFO and RX data to be read from the RX FIFO. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 155 Bit(s) 31:0 Field Name DATA Description DMA Mode (DMAEN set) If TA is clear, the first 32-bit write to this register will control SPIDLEN and SPICS. Subsequent reads and writes will be taken as four-byte data words to be read/written to the FIFOs Poll/Interrupt Mode (DMAEN clear, TA set) Writes to the register write bytes to TX FIFO. Reads from register read bytes from the RX FIFO Type RW Reset 0x0 CLK Register
Synopsis Bit(s) 31:16 15:0 CDIV This register allows the SPI clock rate to be set. Description Reserved - Write as 0, read as don't care Clock Divider SCLK = Core Clock / CDIV If CDIV is set to 0, the divisor is 65536. The divisor must be a power of 2. Odd numbers rounded down. The maximum SPI clock rate is of the APB clock. RW 0x0 Type Reset Field Name DLEN Register
Synopsis Bit(s) 31:16 15:0 LEN This register allows the SPI data length rate to be set. Description Reserved - Write as 0, read as don't care Data Length The number of bytes to transfer. This field is only valid for DMA mode (DMAEN set) and controls how many bytes to transmit (and therefore receive). RW 0x0 Type Reset Field Name 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 156 LTOH Register
Synopsis Bit(s) 31:4 3:0 TOH This register allows the LoSSI output hold delay to be set. Description Reserved - Write as 0, read as don't care This sets the Output Hold delay in APB clocks. A value of 0 causes a 1 clock delay. RW 0x1 Type Reset Field Name DC Register
Synopsis This register controls the generation of the DREQ and Panic signals to an external DMA engine The DREQ signals are generated when the FIFOs reach their defined levels and need servicing. The Panic signals instruct the external DMA engine to raise the priority of its AXI requests. Description DMA Read Panic Threshold. Generate the Panic signal to the RX DMA engine whenever the RX FIFO level is greater than this amount. DMA Read Request Threshold. Generate A DREQ to the RX DMA engine whenever the RX FIFO level is greater than this amount, (RX DREQ is also generated if the transfer has finished but the RXFIFO isn t empty). DMA Write Panic Threshold. Generate the Panic signal to the TX DMA engine whenever the TX FIFO level is less than or equal to this amount. DMA Write Request Threshold. Generate a DREQ signal to the TX DMA engine whenever the TX FIFO level is less than or equal to this amount. Type RW Reset 0x30 Bit(s) 31:24 Field Name RPANIC 23:16 RDREQ RW 0x20 15:8 TPANIC RW 0x10 7:0 TDREQ RW 0x20 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 157 10.6 Software Operation 10.6.1 Polled a) Set CS, CPOL, CPHA as required and set TA = 1. b) Poll TXD writing bytes to SPI_FIFO, RXD reading bytes from SPI_FIFO until all data written. c) Poll DONE until it goes to 1. d) Set TA = 0. 10.6.2 Interrupt e) Set INTR and INTD. These can be left set over multiple operations. f) Set CS, CPOL, CPHA as required and set TA = 1. This will immediately trigger a first interrupt with DONE == 1. g) On interrupt: h) If DONE is set and data to write (this means it is the first interrupt), write up to 16 bytes to SPI_FIFO. If DONE is set and no more data, set TA = 0. Read trailing data from SPI_FIFO until RXD is 0. i) If RXR is set read 12 bytes data from SPI_FIFO and if more data to write, write up to 12 bytes to SPIFIFO. 10.6.3 DMA Note: In order to function correctly, each DMA channel must be set to perform 32-bit transfers when communicating with the SPI. Either the Source or the Destination Transfer Width field in the DMA TI register must be set to 0 (i.e. 32-bit words) depending upon whether the channel is reading or writing to the SPI. Two DMA channels are required, one to read from and one to write to the SPI. j) Enable DMA DREQ's by setting the DMAEN bit and ADCS if required. k) Program two DMA control blocks, one for each DMA controller. l) DMA channel 1 control block should have its PER_MAP set to x and should be set to write `transfer length' + 1 words to SPI_FIFO. The data should comprise: i) A word with the transfer length in bytes in the top sixteen bits, and the control register settings [7:0] in the bottom eight bits (i.e. TA = 1, CS, CPOL, CPHA as required.) ii) `Transfer length' number in words of data to send. m) DMA channel 2 control block should have its PER_MAP set to y and should be set to read `transfer length' words from SPI_FIFO. n) Point each DMA channel at its CB and set its ACTIVE bit to 1. o) On receipt of an interrupt from DMA channel 2, the transfer is complete. 06 F...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.
- Spring '13