Unformatted text preview: ciation (IrDA) Serial InfraRed (SIR) protocol Encoder/Decoder (ENDEC) Direct Memory Access (DMA). The UART provides: Separate 16x8 transmit and 16x12 receive FIFO memory. Programmable baud rate generator. Standard asynchronous communication bits (start, stop and parity). These are added prior to transmission and removed on reception. False start bit detection. Line break generation and detection. Support of the modem control functions CTS and RTS. However DCD, DSR, DTR, and RI are not supported. Programmable hardware flow control. Fully-programmable serial interface characteristics: data can be 5, 6, 7, or 8 bits even, odd, stick, or no-parity bit generation and detection 1 or 2 stop bit generation baud rate generation, dc up to UARTCLK/16 The UART clock source and associated dividers are controlled by the Clock Manager. For the in-depth UART overview, please, refer to the ARM PrimeCell UART (PL011) Revision: r1p5 Technical Reference Manual. 13.1 Variations from the 16C650 UART The UART varies from the industry-standard 16C650 UART device as follows: Receive FIFO trigger levels are 1/8, 1/4, 1/2, 3/4, and 7/8 Transmit FIFO trigger levels are 1/8, 1/4, 1/2, 3/4, and 7/8 The internal register map address space, and the bit function of each register differ
Page 175 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved The deltas of the modem status signals are not available. 1.5 stop bits (1 or 2 stop bits only are supported) Independent receive clock. 13.2 Primary UART Inputs and Outputs The following 16C650 UART features are not supported: The UART has two primary inputs RXD, nCTS and two primary outputs TXD, nRTS. The remaining signals like SRIN, SROUT, OUT1, OUT2, DSR, DTR, and RI are not supported in this implementation. The following table shows the UART signals map on the General Purpose I/O (GPIO). For the insight on how to program alternate function refer to the GPIO paragraph.
Pull GPIO14 GPIO15 GPIO16 GPIO17 GPIO30 GPIO31 GPIO32 GPIO33 GPIO36 GPIO37 GPIO38 GPIO39 Low Low Low Low Low Low Low Low High Low Low Low TXD0 RXD0 RTS0 CTS0 ALT0 TXD0 RXD0 CTS0 RTS0 CTS0 RTS0 TXD0 RXD0 ALT1 ALT2 ALT3 ALT4 ALT5 Table 13-1 UART Assignment on the GPIO Pin map 13.3 UART Interrupts The UART has one intra-chip interrupt UARTINTR generated as the OR-ed function of the five individual interrupts. UARTINTR, this is an OR function of the five individual masked outputs: UARTRXINTR UARTTXINTR UARTRTINTR UARTMSINTR, that can be caused by: -- UARTCTSINTR, because of a change in the nUARTCTS modem status -- UARTDSRINTR, because of a change in the nUARTDSR modem status. UARTEINTR, that can be caused by an error in the reception:
06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 176 -- UARTOEINTR, because of an overrun error -- UARTBEINTR, because of a break in the reception -- UARTPEINTR, because of a parity error in the received character -- UARTFEINTR, because of a framing error in the received character. One can enable or disable the individual interrupts by changing the mask bits in the Interrupt Mask Set/Clear Register, UART_IMSC. Setting the appropriate mask bit HIGH enables the interrupt. UARTRXINTR: The transmit interrupt changes state when one of the following events occurs: If the FIFOs are enabled and the transmit FIFO is equal to or lower than the programmed trigger level then the transmit interrupt is asserted HIGH. The transmit interrupt is cleared by writing data to the transmit FIFO until it becomes greater than the trigger level, or by clearing the interrupt. If the FIFOs are disabled (have a depth of one location) and there is no data present in the transmitters single location, the transmit interrupt is asserted HIGH. It is cleared by performing a single write to the transmit FIFO, or by clearing the interrupt. UARTRTINTR: The receive interrupt changes state when one of the following events occurs: If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level. When this happens, the receive interrupt is asserted HIGH. The receive interrupt is cleared by reading data from the receive FIFO until it becomes less than the trigger level, or by clearing the interrupt. If the FIFOs are disabled (have a depth of one location) and data is received thereby filling the location, the receive interrupt is asserted HIGH. The receive interrupt is cleared by performing a single read of the receive FIFO, or by clearing the interrupt. 13.4 Register View The PL011 USRT is mapped on base adderss 0x7E20100. It has the following memorymapped registers.
UART Address Map Address Register Name Offset 0x0 0x4 0x18 DR RSRECR FR Flag register Description Data Register Size 32 32 32 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 177 0x20 0x24 0x28 0x2c 0x30 0x34 0x38 0x3c 0x40 0x44 0x48 0x80 0x84 0x88 0x8c ILPR IBRD FBRD LCRH CR IFLS IMSC RIS MIS ICR DMACR ITCR ITIP ITOP TDR not in use Integer Ba...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.
- Spring '13