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Unformatted text preview: e 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0xda, 0xdb, 0xdc. 10.3.4 24bit read command A 24 bit read can be achieved by using the command 0x04. 10.3.5 32bit read command A 32bit read can be achieved by using the command 0x09. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 151 10.4 Block Diagram Figure 10-6 Serial interface Block Diagram 10.5 SPI Register Map The BCM2835 devices has only one SPI interface of this type. It is referred to in all the documentation as SPI0. It has two additional mini SPI interfaces (SPI1 and SPI2). The specifiation of those can be found under 2.3 Universal SPI Master (2x). The base address of this SPI0 interface is 0x7E204000. SPI Address Map
Address Offset 0x0 0x4 0x8 Register Name Description SPI Master Control and Status SPI Master TX and RX FIFOs SPI Master Clock Divider Size 32 32 32 CS FIFO CLK 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 152 0xc 0x10 0x14 DLEN LTOH DC SPI Master Data Length SPI LOSSI mode TOH SPI DMA DREQ Controls 32 32 32 CS Register
Synopsis Bit(s) 31:26 25 LEN_LONG This register contains the main control and status bits for the SPI. Description Reserved - Write as 0, read as don't care Enable Long data word in Lossi mode if DMA_LEN is set 0= writing to the FIFO will write a single byte 1= wrirng to the FIFO will write a 32 bit word Enable DMA mode in Lossi mode Chip Select 2 Polarity 0= Chip select is active low. 1= Chip select is active high. Chip Select 1 Polarity 0= Chip select is active low. 1= Chip select is active high. Chip Select 0 Polarity 0= Chip select is active low. 1= Chip select is active high. RXF - RX FIFO Full 0 = RXFIFO is not full. 1 = RX FIFO is full. No further serial data will be sent/ received until data is read from FIFO. RXR RX FIFO needs Reading ( full) 0 = RX FIFO is less than full (or not active TA = 0). 1 = RX FIFO is or more full. Cleared by reading sufficient data from the RX FIFO or setting TA to 0. RW 0x0 Type Reset Field Name 24 23 DMA_LEN CSPOL2 RW RW 0x0 0x0 22 CSPOL1 RW 0x0 21 CSPOL0 RW 0x0 20 RXF RO 0x0 19 RXR RO 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 153 18 TXD TXD TX FIFO can accept Data 0 = TX FIFO is full and so cannot accept more data. 1 = TX FIFO has space for at least 1 byte. RXD RX FIFO contains Data 0 = RX FIFO is empty. 1 = RX FIFO contains at least 1 byte. Done transfer Done 0 = Transfer is in progress (or not active TA = 0). 1 = Transfer is complete. Cleared by writing more data to the TX FIFO or setting TA to 0. Unused Unused LEN LoSSI enable The serial interface is configured as a LoSSI master. 0 = The serial interface will behave as an SPI master. 1 = The serial interface will behave as a LoSSI master. REN Read Enable read enable if you are using bidirectional mode. If this bit is set, the SPI peripheral will be able to send data to this device. 0 = We intend to write to the SPI peripheral. 1 = We intend to read from the SPI peripheral. ADCS Automatically Deassert Chip Select 0 = Don t automatically deassert chip select at the end of a DMA transfer chip select is manually controlled by software. 1 = Automatically deassert chip select at the end of a DMA transfer (as determined by SPIDLEN) INTR Interrupt on RXR 0 = Don t generate interrupts on RX FIFO condition. 1 = Generate interrupt while RXR = 1. INTD Interrupt on Done 0 = Don t generate interrupt on transfer complete. 1 = Generate interrupt when DONE = 1. RO 0x1 17 RXD RO 0x0 16 DONE RO 0x0 15 14 13 TE_EN LMONO LEN RW RW RW 0x0 0x0 0x0 12 REN RW 0x1 11 ADCS RW 0x0 10 INTR RW 0x0 9 INTD RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 154 8 DMAEN DMAEN DMA Enable 0 = No DMA requests will be issued. 1 = Enable DMA operation. Peripheral generates data requests. These will be taken in four-byte words until the SPIDLEN has been reached. Transfer Active 0 = Transfer not active./CS lines are all high (assuming CSPOL = 0). RXR and DONE are 0. Writes to SPIFIFO write data into bits -0 of SPICS allowing DMA data blocks to set mode before sending data. 1 = Transfer active. /CS lines are set according to CS bits and CSPOL. Writes to SPIFIFO write data to TX FIFO.TA is cleared by a dma_frame_end pulse from the DMA controller. Chip Select Polarity 0 = Chip select lines are active low 1 = Chip select lines are active high CLEAR FIFO Clear 00 = No action. x1 = Clear TX FIFO. One shot operation. 1x = Clear RX FIFO. One shot operation. If CLEAR and TA are both set in the same operation, the FIFOs are cleared before the new frame is started. Read back as 0. Clock Polarity 0 = Rest state of clock = low. 1 = Rest state of clock = high. Clock Phase 0 = First SCLK transition at middle of data bit. 1 = First SCLK transition at beginning of data bit. Chip...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.
- Spring '13