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Unformatted text preview: adcom Corporation. All rights reserved Page 37 4 DMA Controller
4.1 Overview The majority of hardware pipelines and peripherals within the BCM2835 are bus masters, enabling them to efficiently satisfy their own data requirements. This reduces the requirements of the DMA controller to block-to-block memory transfers and supporting some of the simpler peripherals. In addition, the DMA controller provides a read only prefetch mode to allow data to be brought into the L2 cache in anticipation of its later use. Beware that the DMA controller is direcly connected to the peripherals. Thus the DMA controller must be set-up to use the Physical (harware) addresses of the peripherals. The BCM2835 DMA Controller provides a total of 16 DMA channels. Each channel operates independently from the others and is internally arbitrated onto one of the 3 system busses. This means that the amount of bandwidth that a DMA channel may consume can be controlled by the arbiter settings. Each DMA channel operates by loading a Control Block (CB) data structure from memory into internal registers. The Control Block defines the required DMA operation. Each Control Block can point to a further Control Block to be loaded and executed once the operation described in the current Control Block has completed. In this way a linked list of Control Blocks can be constructed in order to execute a sequence of DMA operations without software intervention. The DMA supports AXI read bursts to ensure efficient external SDRAM use. The DMA control block contains a burst parameter which indicates the required burst size of certain memory transfers. In general the DMA doesn't do write bursts, although wide writes will be done in 2 beat bursts if possible. Memory-to-Peripheral transfers can be paced by a Data Request (DREQ) signal which is generated by the peripheral. The DREQ signal is level sensitive and controls the DMA by gating its AXI bus requests. A peripheral can also provide a Panic signal alongside the DREQ to indicate that there is an imminent danger of FIFO underflow or overflow or similar critical situation. The Panic is used to select the AXI apriority level which is then passed out onto the AXI bus so that it can be used to influence arbitration in the rest of the system. The allocation of peripherals to DMA channels is programmable. The DMA can deal with byte aligned transfers and will minimise bus traffic by buffering and packing misaligned accesses. Each DMA channel can be fully disabled via a top level power register to save power. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 38 4.2 DMA Controller Registers The DMA Controller is comprised of several identical DMA Channels depending upon the required configuration. Each individual DMA channel has an identical register map (although LITE channels have less functionality and hence less registers). DMA Channel 0 is located at the address of 0x7E007000, Channel 1 at 0x7E007100, Channel 2 at 0x7E007200 and so on. Thus adjacent DMA Channels are offset by 0x100. DMA Channel 15 however, is physically removed from the other DMA Channels and so has a different address base of 0x7EE05000. DMA Channel Offsets DMA Channels 0 14 Register Set Offsets from DMA0_BASE 0x000 0x100 0x200 0x300 0x400 0x500 0x600 0x700 0x800 0x900 0xa00 0xb00 0xc00 0xd00 0xe00 DMA Channel 0 Register Set DMA Channel 1 Register Set DMA Channel 2 Register Set DMA Channel 3 Register Set DMA Channel 4 Register Set DMA Channel 5 Register Set DMA Channel 6 Register Set DMA Channel 7 Register Set DMA Channel 8 Register Set DMA Channel 9 Register Set DMA Channel 10 Register Set DMA Channel 11 Register Set DMA Channel 12 Register Set DMA Channel 13 Register Set DMA Channel 14 Register Set DMA Channel 15 Register Set Offset from DMA15_BASE 0x000 DMA Channel 15 Register Set Table 4-1 DMA Controller Register Address Map 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 39 4.2.1 DMA Channel Register Address Map Each DMA channel has an identical register map, only the base address of each channel is different. There is a global enable register at the top of the Address map that can disable each DMA for powersaving. Only three registers in each channels register set are directly writeable (CS, CONBLK_AD and DEBUG). The other registers (TI, SOURCE_AD, DEST_AD, TXFR_LEN, STRIDE & NEXTCONBK), are automatically loaded from a Control Block data structure held in external memory.
220.127.116.11 Control Block Data Structure Control Blocks (CB) are 8 words (256 bits) in length and must start at a 256-bit aligned address. The format of the CB data structure in memory, is shown below. Each 32 bit word of the control block is automatically loaded into the corresponding 32 bit DMA control block register at the start of a DMA transfer. The descriptions of these registers also defines the cor...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.
- Spring '13