Broadcom BCM2835

406 science park milton road cambridge cb4 0ww 2012

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Unformatted text preview: ignore 1 = stop Reserved - Write as 0, read as don't care HCTL_8BIT Use 8 data lines: 0 = disabled 1 = enabled RW 0x0 RW 0x0 Type Reset Bit(s) 31:23 22 Field Name 21 BOOT_EN RW 0x0 20 SPI_MODE RW 0x0 19 GAP_IEN RW 0x0 18 READWAIT_EN RW 0x0 17 GAP_RESTART RW 0x0 16 GAP_STOP RW 0x0 15:6 5 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 73 4:3 2 HCTL_HS_EN Reserved - Write as 0, read as don't care Select high speed mode (i.e. DAT and CMD lines change on the rising CLK edge): 0 = disabled 1 = enabled Use 4 data lines: 0 = disabled 1 = enabled Reserved - Write as 0, read as don't care RW 0x0 1 HCTL_DWIDTH RW 0x0 0 CONTROL1 Register Synopsis This register is used to configure the EMMC module. For the exact details please refer to the Arasan documentation SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf. Bits marked as reserved in this document but not by the Arasan documentation refer to functionality which has been disabled due to the changes listed in the previous chapter. CLK_STABLE seems contrary to its name only to indicate that there was a rising edge on the clk_emmc input but not that the frequency of this clock is actually stable. Description Reserved - Write as 0, read as don't care SRST_DATA Reset the data handling circuit: 0 = disabled 1 = enabled Reset the command handling circuit: 0 = disabled 1 = enabled Reset the complete host circuit: 0 = disabled 1 = enabled Reserved - Write as 0, read as don't care DATA_TOUNIT Data timeout unit exponent: 1111 = disabled x = TMCLK * 2^(x+13) SD clock base divider LSBs RW 0x0 RW 0x0 Type Reset Bit(s) 31:27 26 Field Name 25 SRST_CMD RW 0x0 24 SRST_HC RW 0x0 23:20 19:16 15:8 CLK_FREQ8 RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 74 7:6 5 CLK_FREQ_MS2 CLK_GENSEL SD clock base divider MSBs Mode of clock generation: 0 = divided 1 = programmable Reserved - Write as 0, read as don't care RW RW 0x0 0x0 4:3 2 CLK_EN SD clock enable: 0 = disabled 1 = enabled SD clock stable: 0 = no 1 = yes Clock enable for internal EMMC clocks for power saving: 0 = disabled 1 = enabled RW 0x0 1 CLK_STABLE RO 0x0 0 CLK_INTLEN RW 0x0 INTERRUPT Register Synopsis This register holds the interrupt flags. Each flag can be disabled using the according bit in the IRPT_MASK register. For the exact details please refer to the Arasan documentation SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf. Bits marked as reserved in this document but not by the Arasan documentation refer to functionality which has been disabled due to the changes listed in the previous chapter. ERR is a generic flag and is set if any of the enabled error flags is set. Description Reserved - Write as 0, read as don't care ACMD_ERR Auto command error: 0 = no error 1 = error Reserved - Write as 0, read as don't care DEND_ERR End bit on data line not 1: 0 = no error 1 = error RW 0x0 RW 0x0 Type Reset Bit(s) 31:25 24 Field Name 23 22 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 75 21 DCRC_ERR Data CRC error: 0 = no error 1 = error Timeout on data line: 0 = no error 1 = error Incorrect command index in response: 0 = no error 1 = error End bit on command line not 1: 0 = no error 1 = error Command CRC error: 0 = no error 1 = error Timeout on command line: 0 = no error 1 = error An error has occured: 0 = no error 1 = error Boot operation has terminated: 0 = no 1 = yes Boot acknowledge has been received: 0 = no 1 = yes Clock retune request was made: 0 = no 1 = yes Reserved - Write as 0, read as don't care RW 0x0 20 DTO_ERR RW 0x0 19 CBAD_ERR RW 0x0 18 CEND_ERR RW 0x0 17 CCRC_ERR RW 0x0 16 CTO_ERR RW 0x0 15 ERR RO 0x0 14 ENDBOOT RW 0x0 13 BOOTACK RW 0x0 12 RETUNE RO 0x0 11:9 8 CARD Card made interrupt request: 0 = no 1 = yes Reserved - Write as 0, read as don't care RO 0x0 7:6 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 76 5 READ_RDY DATA register contains data to be read: 0 = no 1 = yes Data can be written to DATA register: 0 = no 1 = yes Reserved - Write as 0, read as don't care RW 0x0 4 WRITE_RDY RW 0x0 3 2 BLOCK_GAP Data transfer has stopped at block gap: 0 = no 1 = yes Data transfer has finished: 0 = no 1 = yes Command has finished: 0 = no 1 = yes RW 0x0 1 DATA_DONE RW 0x0 0 CMD_DONE RW 0x0 IRPT_MASK Register Synopsis This register is used to mask the interrupt flags in the INTERRUPT register. For the exact details please refer to the Arasan documentation SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf. Bits marked as reserved in this document but not by the Arasan documentation refer to functionality which has been disabled due to the changes listed in the previous chapter. Description Reserved - Write as 0, read as don't care ACMD_ERR Set flag if auto command error: 0 = no 1 = yes Reserved - Write as 0, read as don't care DEND_ERR Set flag if end bit on data line not 1: 0 = no 1 = yes RW 0x0 RW 0x0 Type Reset Bit(s) 31:25 24 Field Name 23 22 06 February 2012 Broadc...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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