Broadcom BCM2835

406 science park milton road cambridge cb4 0ww 2012

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Unformatted text preview: om Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 77 21 DCRC_ERR Set flag if data CRC error: 0 = no 1 = yes Set flag if timeout on data line: 0 = no 1 = yes Set flag if incorrect command index in response: 0 = no 1 = yes Set flag if end bit on command line not 1: 0 = no 1 = yes Set flag if command CRC error: 0 = no 1 = yes Set flag if timeout on command line: 0 = no 1 = yes Reserved - Write as 0, read as don't care RW 0x0 20 DTO_ERR RW 0x0 19 CBAD_ERR RW 0x0 18 CEND_ERR RW 0x0 17 CCRC_ERR RW 0x0 16 CTO_ERR RW 0x0 15 14 ENDBOOT Set flag if boot operation has terminated: 0 = no 1 = yes Set flag if boot acknowledge has been received: 0 = no 1 = yes Set flag if clock retune request was made: 0 = no 1 = yes Reserved - Write as 0, read as don't care RW 0x0 13 BOOTACK RW 0x0 12 RETUNE RW 0x0 11:9 8 CARD Set flag if card made interrupt request: 0 = no 1 = yes Reserved - Write as 0, read as don't care RW 0x0 7:6 5 READ_RDY Set flag if DATA register contains data to be read: 0 = no 1 = yes RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 78 4 WRITE_RDY Set flag if data can be written to DATA register: 0 = no 1 = yes Reserved - Write as 0, read as don't care RW 0x0 3 2 BLOCK_GAP Set flag if data transfer has stopped at block gap: 0 = no 1 = yes Set flag if data transfer has finished: 0 = no 1 = yes Set flag if command has finished: 0 = no 1 = yes RW 0x0 1 DATA_DONE RW 0x0 0 CMD_DONE RW 0x0 IRPT_EN Register Synopsis This register is used to enable the different interrupts in the INTERRUPT register to generate an interrupt on the int_to_arm output. For the exact details please refer to the Arasan documentation SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf. Bits marked as reserved in this document but not by the Arasan documentation refer to functionality which has been disabled due to the changes listed in the previous chapter. Description Reserved - Write as 0, read as don't care ACMD_ERR Create interrupt if auto command error: 0 = no 1 = yes Reserved - Write as 0, read as don't care DEND_ERR Create interrupt if end bit on data line not 1: 0 = no 1 = yes Create interrupt if data CRC error: 0 = no 1 = yes RW 0x0 RW 0x0 Type Reset Bit(s) 31:25 24 Field Name 23 22 21 DCRC_ERR RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 79 20 DTO_ERR Create interrupt if timeout on data line: 0 = no 1 = yes Create interrupt if incorrect command index in response: 0 = no 1 = yes Create interrupt if end bit on command line not 1: 0 = no 1 = yes Create interrupt if command CRC error: 0 = no 1 = yes Create interrupt if timeout on command line: 0 = no 1 = yes Reserved - Write as 0, read as don't care RW 0x0 19 CBAD_ERR RW 0x0 18 CEND_ERR RW 0x0 17 CCRC_ERR RW 0x0 16 CTO_ERR RW 0x0 15 14 ENDBOOT Create interrupt if boot operation has terminated: 0 = no 1 = yes Create interrupt if boot acknowledge has been received: 0 = no 1 = yes Create interrupt if clock retune request was made: 0 = no 1 = yes Reserved - Write as 0, read as don't care RW 0x0 13 BOOTACK RW 0x0 12 RETUNE RW 0x0 11:9 8 CARD Create interrupt if card made interrupt request: 0 = no 1 = yes Reserved - Write as 0, read as don't care RW 0x0 7:6 5 READ_RDY Create interrupt if DATA register contains data to be read: 0 = no 1 = yes RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 80 4 WRITE_RDY Create interrupt if data can be written to DATA register: 0 = no 1 = yes Reserved - Write as 0, read as don't care RW 0x0 3 2 BLOCK_GAP Create interrupt if data transfer has stopped at block gap: 0 = no 1 = yes Create interrupt if data transfer has finished: 0 = no 1 = yes Create interrupt if command has finished: 0 = no 1 = yes RW 0x0 1 DATA_DONE RW 0x0 0 CMD_DONE RW 0x0 CONTROL2 Register Synopsis This register is used to enable the different interrupts in the INTERRUPT register to generate an interrupt on the int_to_arm output. For the exact details please refer to the Arasan documentation SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf. Bits marked as reserved in this document but not by the Arasan documentation refer to functionality which has been disabled due to the changes listed in the previous chapter. Description Reserved - Write as 0, read as don't care TUNED Tuned clock is used for sampling data: 0 = no 1 = yes Start tuning the SD clock: 0 = not tuned or tuning complete 1 = tuning Reserved - Write as 0, read as don't care RW 0x0 Type Reset Bit(s) 31:24 23 Field Name 22 TUNEON RW 0x0 21:19 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 81 18:16 UHSMODE Select the speed mode of the SD card: 000 = SDR12 001 = SDR25 010 = SDR50 011 = SDR104 100 = DDR50 other = reserved Reserved - Write as 0, read as don't care RW 0x0 15:8 7 NOTC12_ERR Error occurred during auto command CMD12 execution: 0 = no error 1 = error Reserved - Write as 0, read as don't care RO 0x0 6:5 4 ACBAD_ERR Command index error occurred during auto command execution: 0 = no error 1 = error End bit is not 1 during auto command execution: 0 = no error 1 = error Command CRC error occurred during auto command execution: 0 = no error 1 = error Timeout occurred during au...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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