Broadcom BCM2835

406 science park milton road cambridge cb4 0ww 2012

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Unformatted text preview: ebruary 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 158 10.6.4 Notes 1. The SPI Master knows nothing of the peripherals it is connected to. It always both sends and receives bytes for every byte of the transaction. 2. SCLK is only generated during byte serial transfer. It pauses in the rest state if the next byte to send is not ready or RXF is set. 3. Setup and Hold times related to the automatic assertion and de-assertion of the CS lines when operating in DMA mode (DMAEN and ADCS set) are as follows: The CS line will be asserted at least 3 core clock cycles before the msb of the first byte of the transfer. The CS line will be de-asserted no earlier than 1 core clock cycle after the trailing edge of the final clock pulse. If these parameters are insufficient, software control should alleviate the problem. ADCS should be 0 allowing software to manually control the assertion and de-assertion of the CS lines. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 159 11 SPI/BSC SLAVE 11.1 Introduction The BSC interface can be used as either a Broadcom Serial Controller (BSC) or a Serial Peripheral Interface (SPI) controller. The BSC bus is a proprietary bus compliant with the Philips I2C bus/interface version 2.1 January 2000. Both BSC and SPI controllers work in the slave mode. The BSC slave controller has specially built in the Host Control and Software Registers for a Chip booting. The BCS controller supports fast-mode (400Kb/s) and it is compliant to the I2C bus specification version 2.1 January 2000 with the restrictions: I2C slave only operation clock stretching is not supported 7-bit addressing only There is only one BSC/SPI slave. The registers base addresses is 0x7E21_4000. 11.2 Registers The SPI controller implements 3 wire serial protocol variously called Serial Peripheral Interface (SPI) or Synchronous Serial Protocol (SSP). BSC and SPI controllers do not have DMA connected, hence DMA is not supported. I2C_SPI_SLV Address Map Address Offset 0x0 0x4 0x8 Register Name Description Data Register The operation status register and error clear register The I2C SPI Address Register holds the I2C slave address value The Control register is used to configure the I2C or SPI operation Flag register Interrupt fifo level select register Interupt Mask Set Clear Register Size 32 32 32 DR RSR SLV 0xc CR 32 0x10 0x14 0x18 FR IFLS IMSC 32 32 32 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 160 0x1c 0x20 0x24 0x28 0x2c 0x30 0x34 0x38 0x3c RIS MIS ICR DMACR TDR GPUSTAT HCTRL DEBUG1 DEBUG2 Raw Interupt Status Register Masked Interupt Status Register Interupt Clear Register DMA Control Register FIFO Test Data GPU Status Register Host Control Register I2C Debug Register SPI Debug Register 32 32 32 32 32 32 32 32 32 DR Register Synopsis The I2C SPI Data Register is used to transfer/receive data characters and provide a Status and Flag information. Status and Flag information is also available via individual registers. Description RXFLEVEL RX FIFO Level Returns the current level of the RX FIFO use TXFLEVEL TX FIFO Level Returns the current level of the TX FIFO use RXBUSY Receive Busy 0 Receive operation inactive 1 Receive operation in operation TXFE TX FIFO Empty 0 TX FIFO is not empty 1 When TX FIFO is empty RXFE RX FIFO Full 0 FX FIFO is not full 1 When FX FIFO is full Type RO Reset 0x0 Bit(s) 31:27 Field Name RXFLEVEL 26:22 TXFLEVEL RO 0x0 21 RXBUSY RO 0x0 20 TXFE RO 0x1 19 RXFF RO 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 161 18 TXFF TXFF TX FIFO Full 0 TX FIFO is not full 1 When TX FIFO is full RXFE RX FIFO Empty 0 FX FIFO is not empty 1 When FX FIFO is empty TXBUSY Transmit Busy 0 Transmit operation inactive 1 Transmit operation in operation Reserved - Write as 0, read as don't care RO 0x0 17 RXFE RO 0x1 16 TXBUSY RO 0x0 15:10 9 UE TXUE TX Underrun Error 0 - No error case detected 1 Set when TX FIFO is empty and I2C master attempt to read a data character from I2C slave. Cleared by writing 0 to I2C SPI Status register . RXOE RX Overrun Error 0 No error case detected 1 Set when RX FIFO is full and a new data character is received. Cleared by writing 0 to I2C SPI Status register . DATA Received/Transferred data characters Data written to this location is pushed into the TX FIFO. Data read from this location is fetched from the RX FIFO. RO 0x0 8 OE RO 0x0 7:0 DATA RW 0x0 RSR Register Synopsis Bit(s) 31:6 5 4 3 RXDMABREQ RXDMAPREQ TXDMABREQ The operation status register and error clear register. Description Reserved - Write as 0, read as don't care Unsupported, write zero, read as don't care Unsupported, write zero, read as don't care Unsupported, write zero, read as don't care RO RO RO 0x0 0x0 0x0 Type Reset Field Name 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 162 2 1 TXDMAPREQ UE Unsupported, write zero, read as...
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