Broadcom BCM2835

406 science park milton road cambridge cb4 0ww 2012

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Unformatted text preview: 0x0 8 PEMIS RW 0x0 7 FEMIS RW 0x0 6 RTMIS RW 0x0 5 TXMIS RW 0x0 4 RXMIS RW 0x0 3 2 1 DSRMMIS DCDMMIS CTSMMIS RW RW RW 0x0 0x0 0x0 0 RIMMIS RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 191 ICR Register Synopsis The UART_ICR Register is the interrupt clear register. Bit(s) Field Name 31:11 10 OEIC Description Reserved - Write as 0, read as don't care Overrun error interrupt clear. Clears the UARTOEINTR interrupt. Break error interrupt clear. Clears the UARTBEINTR interrupt. Parity error interrupt clear. Clears the UARTPEINTR interrupt. Framing error interrupt clear. Clears the UARTFEINTR interrupt.. Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. Transmit interrupt clear. Clears the UARTTXINTR interrupt. Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. Unsupported, write zero, read as don't care Unsupported, write zero, read as don't care nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. Unsupported, write zero, read as don't care Type Reset RW 0x0 9 BEIC RW 0x0 8 PEIC RW 0x0 7 FEIC RW 0x0 6 RTIC RW 0x0 5 TXIC RW 0x0 4 RXIC RW 0x0 3 2 1 DSRMIC DCDMIC CTSMIC RW RW RW 0x0 0x0 0x0 0 RIMIC RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 192 DMACR Register Synopsis This is the disabled DMA Control Register, writing to it has not effect and reading returns 0. Bit(s) Field Name 31:3 2 1 0 DMAONERR TXDMAE RXDMAE Description Reserved - Write as 0, read as don't care Unsupported, write zero, read as don't care Unsupported, write zero, read as don't care Unsupported, write zero, read as don't care RW RW RW 0x0 0x0 0x0 Type Reset ITCR Register Synopsis This is the Test Control Register UART_ITCR. Bit(s) Field Name 31:2 1 ITCR1 Description Reserved - Write as 0, read as don't care Test FIFO enable. When this bit it 1, a write to the Test Data Register, UART_DR writes data into the receive FIFO, and reads from the UART_DR register reads data out of the transmit FIFO. When this bit is 0, data cannot be read directly from the transmit FIFO or written directly to the receive FIFO (normal operation). Integration test enable. When this bit is 1, the UART is placed in integration test mode, otherwise it is in normal operation. Type Reset RW 0x0 0 ITCR0 RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 193 ITIP Register Synopsis This is the Test Control Register UART_ITIP. Bit(s) Field Name 31:4 3 ITIP3 Description Reserved - Write as 0, read as don't care Reads return the value of the nUARTCTS primary input. Reserved - Write as 0, read as don't care Type Reset RW 0x0 2:1 0 ITIP0 Reads return the value of the UARTRXD primary input. RW 0x0 ITOP Register Synopsis This is the Test Control Register UART_ITOP. Bit(s) Field Name 31:12 11 ITOP11 Description Reserved - Write as 0, read as don't care Intra-chip output. Writes specify the value to be driven on UARTMSINTR. Reads return the value of UARTMSINTR at the output of the test multiplexor. Intra-chip output. Writes specify the value to be driven on UARTRXINTR. Reads return the value of UARTRXINTR at the output of the test multiplexor. Intra-chip output. Writes specify the value to be driven on UARTTXINTR. Reads return the value of UARTTXINTR at the output of the test multiplexor. Type Reset RW 0x0 10 ITOP10 RW 0x0 9 ITOP9 RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 194 8 ITOP8 Intra-chip output. Writes specify the value to be driven on UARTRTINTR. Reads return the value of UARTRTINTR at the output of the test multiplexor. Intra-chip output. Writes specify the value to be driven on UARTEINTR. Reads return the value of UARTEINTR at the output of the test multiplexor. Intra-chip output. Writes specify the value to be driven on UARTINTR. Reads return the value of UARTINTR at the output of the test multiplexor. Reserved - Write as 0, read as don't care RW 0x0 7 ITOP7 RW 0x0 6 ITIP6 RW 0x0 5:4 3 ITIP3 Primary output. Writes specify the value to be driven on nUARTRTS. Reserved - Write as 0, read as don't care RW 0x0 2:1 0 ITIP0 Primary output. Writes specify the value to be driven on UARTTXD. RW 0x0 TDR Register Synopsis UART_TDR is the test data register. It enables data to be written into the receive FIFO and read out from the transmit FIFO for test purposes. This test function is enabled by the ITCR1bit in the Test Control Register, UART_ITCR. Bit(s) Field Name 31:11 10:0 TDR10_0 Description Reserved - Write as 0, read as don't care When the ITCR1 bit is set to 1, data is written into the receive FIFO and read out of the transmit FIFO. RW 0x0 Type Reset 06 February 2012 Broadcom Europe Ltd. 4...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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