Broadcom BCM2835

406 science park milton road cambridge cb4 0ww 2012

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Unformatted text preview: 8_TXFR_LEN 9_TXFR_LEN 10_TXFR_LEN 11_TXFR_LEN 12_TXFR_LEN 13_TXFR_LEN 14_TXFR_LEN Register Synopsis Bit(s) 31:16 15:0 XLENGTH DMA Transfer Length Description Reserved - Write as 0, read as don't care Transfer Length Length of transfer, in bytes. Updated by the DMA engine as the transfer progresses. RW 0x0 Type Reset Field Name 7_DEBUG 8_DEBUG 9_DEBUG 10_DEBUG 11_DEBUG 12_DEBUG 13_DEBUG 14_DEBUG Register Synopsis Bit(s) DMA Lite Debug register. Description Type Reset Field Name 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 57 31:29 28 LITE Reserved - Write as 0, read as don't care DMA Lite Set if the DMA is a reduced performance LITE engine. DMA Version DMA version number, indicating control bit filed changes. DMA State Machine State Returns the value of the DMA engines state machine for this channel. DMA ID Returns the DMA AXI ID of this DMA channel. DMA Outstanding Writes Counter Returns the number of write responses that have not yet been received. This count is reset at the start of each new DMA transfer or with a DMA reset. Reserved - Write as 0, read as don't care READ_ERROR Slave Read Response Error Set if the read operation returned an error value on the read response bus. It can be cleared by writing a 1, Fifo Error Set if the optional read Fifo records an error condition. It can be cleared by writing a 1, Read Last Not Set Error If the AXI read last signal was not set when expected, then this error bit will be set. It can be cleared by writing a 1. RW 0x0 RO 0x1 27:25 VERSION RO 0x2 24:16 DMA_STATE RO 0x0 15:8 DMA_ID RO 0x0 7:4 OUTSTANDING_WRITES RO 0x0 3 2 1 FIFO_ERROR RW 0x0 0 READ_LAST_NOT_SET_ERROR RW 0x0 INT_STATUS Register Synopsis Bit(s) Interrupt status of each DMA engine Description Type Reset Field Name 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 58 31:16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT15 INT14 INT13 INT12 INT11 INT10 INT9 INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 Reserved - Write as 0, read as don't care Interrupt status of DMA engine 15 Interrupt status of DMA engine 14 Interrupt status of DMA engine 13 Interrupt status of DMA engine 12 Interrupt status of DMA engine 11 Interrupt status of DMA engine 10 Interrupt status of DMA engine 9 Interrupt status of DMA engine 8 Interrupt status of DMA engine 7 Interrupt status of DMA engine 6 Interrupt status of DMA engine 5 Interrupt status of DMA engine 4 Interrupt status of DMA engine 3 Interrupt status of DMA engine 2 Interrupt status of DMA engine 1 Interrupt status of DMA engine 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 ENABLE Register Synopsis Bit(s) 31:15 Global enable bits for each channel Description Reserved - Write as 0, read as don't care Type Reset Field Name 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 59 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN14 EN13 EN12 EN11 EN10 EN9 EN8 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 enable dma engine 14 enable dma engine 13 enable dma engine 12 enable dma engine 11 enable dma engine 10 enable dma engine 9 enable dma engine 8 enable dma engine 7 enable dma engine 6 enable dma engine 5 enable dma engine 4 enable dma engine 3 enable dma engine 2 enable dma engine 1 enable dma engine 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 60 4.2.1.3 Peripheral DREQ Signals A DREQ (Data Request) mechanism is used to pace the data flow between the DMA and a peripheral. Each peripheral is allocated a permanent DREQ signal. Each DMA channel can select which of the DREQ signals should be used to pace the transfer by controlling the DMA reads, DMA writes or both. Note that DREQ 0 is permanently enabled and can be used if no DREQ is required. When a DREQ signal is being used to pace the DMA reads, the DMA will wait until it has sampled DREQ high before launching a single or burst read operation. It will then wait for all the read data to be returned before re-checking the DREQ and starting the next read. Thus once a peripheral receives the read request it should remove its DREQ as soon as possible to prevent the DMA from re-sampling the same DREQ assertion. DREQ's are not required when reading from AXI peripherals. In this case, the DMA will request data from the peripheral and the peripheral will only send the data when it is available. The DMA will not request data that is does not have room for, so no pacing of the data flow is required. DREQ's are required when reading from APB peripherals as the AXI-to-APB bridge will not wait for an APB peripheral to be ready and will just perfom the APB read regardless. Thus an APB peripheral needs to make sure tha...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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