Broadcom BCM2835

63 from the gpu side some of these interrupts are

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Unformatted text preview: it(s) 31:0 R/W Address: 0x210 Function Reset: 0x000 R/Wbs Set to enable IRQ source 31:0 (See IRQ table above) Writing a 1 to a bit will set the corresponding IRQ enable bit. All other IRQ enable bits are unaffected. Only bits which are enabled can be seen in the interrupt pending registers. There is no provision here to see if there are interrupts which are pending but not enabled. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 116 Interrupt enable register 2. Name: IRQ enable 2 Bit(s) 31:0 R/W Address: 0x214 Function Reset: 0x000 R/Wbs Set to enable IRQ source 63:32 (See IRQ table above) Writing a 1 to a bit will set the corresponding IRQ enable bit. All other IRQ enable bits are unaffected. Only bits which are enabled can be seen in the interrupt pending registers. There is no provision here to see if there are interrupts which are pending but not enabled. Base Interrupt enable register. Name: IRQ enable 3 Bit(s) 31:8 7 6 5 4 3 2 1 0 R/W R/Wbs <Unused> R/Wbs Set to enable Access error type -0 IRQ R/Wbs Set to enable Access error type -1 IRQ R/Wbs Set to enable GPU 1 Halted IRQ R/Wbs Set to enable GPU 0 Halted IRQ R/Wbs R/Wbs R/Wbs R/Wbs Set to enable ARM Doorbell 1 IRQ Set to enable ARM Doorbell 0 IRQ Set to enable ARM Mailbox IRQ Set to enable ARM Timer IRQ Address: 0x218 Function Reset: 0x000 Writing a 1 to a bit will set the corresponding IRQ enable bit. All other IRQ enable bits are unaffected. Again only bits which are enabled can be seen in the basic pending register. There is no provision here to see if there are interrupts which are pending but not enabled. Interrupt disable register 1. Name: IRQ disable 1 Bit(s) 31:0 R/W Address: 0x21C Function Reset: 0x000 R/Wbc Set to disable IRQ source 31:0 (See IRQ table above) Writing a 1 to a bit will clear the corresponding IRQ enable bit. All other IRQ enable bits are unaffected. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 117 Interrupt disable register 2. Name: IRQ disable 2 Bit(s) 31:0 R/W Address: 0x220 Function Reset: 0x000 R/Wbc Set to disable IRQ source 63:32 (See IRQ table above) Writing a 1 to a bit will clear the corresponding IRQ enable bit. All other IRQ enable bits are unaffected. Base disable register. Name: IRQ disable 3 Bit(s) 31:8 7 6 5 4 3 2 1 0 R/W <Unused> Address: 0x224 Function Reset: 0x000 R/Wbc Set to disable Access error type -0 IRQ R/Wbc Set to disable Access error type -1 IRQ R/Wbc Set to disable GPU 1 Halted IRQ R/Wbc Set to disable GPU 0 Halted IRQ R/Wbc R/Wbc R/Wbc R/Wbc Set to disable ARM Doorbell 1 IRQ Set to disable ARM Doorbell 0 IRQ Set to disable ARM Mailbox IRQ Set to disable ARM Timer IRQ Writing a 1 to a bit will clear the corresponding IRQ enable bit. All other IRQ enable bits are unaffected. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 118 8 PCM / I2S Audio The PCM audio interface is an APB peripheral providing input and output of telephony or high quality serial audio streams. It supports many classic PCM formats including I2S. The PCM audio interface has 4 interface signals; PCM_CLK PCM_FS PCM_DIN - bit clock. - frame sync signal. - serial data input. PCM_DOUT - serial data output. PCM is a serial format with a single bit data_in and single bit data_out. Data is always serialised MS-bit first. The frame sync signal (PCM_FS) is used to delimit the serial data into individual frames. The length of the frame and the size and position of the frame sync are fully programmable. Frames can contain 1 or 2 audio/data channels in each direction. Each channel can be between 8 and 32 bits wide and can be positioned anywhere within the frame as long as the two channels don't overlap. The channel format is separately programmable for transmit and receive directions. PCM_CLK PCM_FS FSLEN FLEN CH1WID PCM_DIN MS Ch. 1 LS MS CH2WID Ch. 2 LS CH1POS CH2POS CH1WID PCM_DOUT MS Ch. 1 LS MS CH2WID Ch. 2 LS CH1POS CH2POS Figure 8-1 PCM Audio Interface Typical Timing The PCM_CLK can be asynchronous to the bus APB clock and can be logically inverted if required. The direction of the PCM_CLK and PCM_FS signals can be individually selected, allowing the interface to act as a master or slave device. The input interface is also capable of supporting up to 2 PDM microphones, as an alternative to the classic PCM input format, in conjunction with a PCM output. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 119 8.1 Block Diagram Figure 8-2 PCM Audio Interface Block Diagram The PCM audio interface contains separate transmit and receive FIFOs. Note that if the frame contains two data channels, they must share the same FIFO and so the channel data will be interleaved. The block can be driven using simple polling, an interrupt based method or dire...
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