Broadcom BCM2835

7 this is the offset which needs to be added to the

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Unformatted text preview: R/W R Function <unused> GPU IRQ 62 Page 113 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Name: IRQ pend base 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R R R R R GPU IRQ 57 GPU IRQ 56 GPU IRQ 55 GPU IRQ 54 GPU IRQ 53 GPU IRQ 19 GPU IRQ 18 GPU IRQ 10 GPU IRQ 9 GPU IRQ 7 Address: 0x200 Reset: 0x000 One or more bits set in pending register 2 One or more bits set in pending register 1 Illegal access type 0 IRQ pending Illegal access type 1 IRQ pending GPU1 halted IRQ pending GPU0 halted IRQ pending (Or GPU1 halted if bit 10 of control register 1 is set) ARM Doorbell 1 IRQ pending ARM Doorbell 0 IRQ pending ARM Mailbox IRQ pending ARM Timer IRQ pending GPU IRQ x (10,11..20) These bits are direct interrupts from the GPU. They have been selected as interrupts which are most likely to be useful to the ARM. The GPU interrupt selected are 7, 9, 10, 18, 19, 53,54,55,56,57,62. For details see the GPU interrupts table. Bits set in pending registers (8,9) These bits indicates if there are bits set in the pending 1/2 registers. The pending 1/2 registers hold ALL interrupts 0..63 from the GPU side. Some of these 64 interrupts are also connected to the basic pending register. Any bit set in pending register 1/2 which is NOT connected to the basic pending register causes bit 8 or 9 to set. Status bits 8 and 9 should be seen as "There are some interrupts pending which you don't know about. They are in pending register 1 /2." Illegal access type-0 IRQ (7) This bit indicate that the address/access error line from the ARM processor has generated an interrupt. That signal is asserted when either an address bit 31 or 30 was high or when an access was 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 114 seen on the ARM Peripheral bus. The status of that signal can be read from Error/HALT status register bit 2. Illegal access type-1 IRQ (6) This bit indicates that an address/access error is seen in the ARM control has generated an interrupt. That can either be an address bit 29..26 was high or when a burst access was seen on the GPU Peripheral bus. The status of that signal can be read from Error/HALT status register bits 0 and 1. GPU-1 halted IRQ (5) This bit indicate that the GPU-1 halted status bit has generated an interrupt. The status of that signal can be read from Error/HALT status register bits 4. GPU-0 (or any GPU) halted IRQ (4) This bit indicate that the GPU-0 halted status bit has generated an interrupt. The status of that signal can be read from Error/HALT status register bits 3. In order to allow a fast interrupt (FIQ) routine to cope with GPU 0 OR GPU-1 there is a bit in control register 1 which, if set will also route a GPU-1 halted status on this bit. Standard peripheral IRQs (0,1,2,3) These bits indicate if an interrupt is pending for one of the ARM control peripherals. GPU pending 1 register. Name: IRQ pend base Bit(s) 31:0 R/W R Address: 0x204 Function IRQ pending source 31:0 (See IRQ table above) Reset: 0x000 This register holds ALL interrupts 0..31 from the GPU side. Some of these interrupts are also connected to the basic pending register. Any interrupt status bit in here which is NOT connected to the basic pending will also cause bit 8 of the basic pending register to be set. That is all bits except 7, 9, 10, 18, 19. GPU pending 2 register. Name: IRQ pend base Bit(s) 31:0 R/W R Address: 0x208 Function IRQ pending source 63:32 (See IRQ table above) Reset: 0x000 This register holds ALL interrupts 32..63 from the GPU side. Some of these interrupts are also connected to the basic pending register. Any interrupt status bit in here which is NOT connected to the basic pending will also cause bit 9 of the basic pending register to be set. That is all bits except . register bits 21..25, 30 (Interrupts 53..57,62). FIQ register. The FIQ register control which interrupt source can generate a FIQ to the ARM. Only a single interrupt can be selected. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 115 Name: FIQ Bit(s) 31:8 7 R/W R R <unused> Address: 0x20C Function Reset: 0x000 FIQ enable. Set this bit to 1 to enable FIQ generation. If set to 0 bits 6:0 are don't care. 6:0 R/W Select FIQ Source FIQ Source. The FIQ source values 0-63 correspond to the GPU interrupt table. (See above) The following values can be used to route ARM specific interrupts to the FIQ vector/routine: FIQ index 0-63 64 65 66 67 68 69 70 71 72-127 Source GPU Interrupts (See GPU IRQ table) ARM Timer interrupt ARM Mailbox interrupt ARM Doorbell 0 interrupt ARM Doorbell 1 interrupt GPU0 Halted interrupt (Or GPU1) GPU1 Halted interrupt Illegal access type-1 interrupt Illegal access type-0 interrupt Do Not Use Interrupt enable register 1. Name: IRQ enable 1 B...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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