Broadcom BCM2835

All new control bits start from bit 8 upwards

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Unformatted text preview: f the value register has finished counting down to zero. The timer pre-divider register: Name: pre-divide Address: base + 0x41C Bit(s) R/W Function 31:10 <Unused> 9:0 R/W Pre-divider value. The Pre-divider register is not present in the SP804. Reset: 0x07D 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 198 The pre-divider register is 10 bits wide and can be written or read from. This register has been added as the SP804 expects a 1MHz clock which we do not have. Instead the pre-divider takes the APB clock and divides it down according to: timer_clock = apb_clock/(pre_divider+1) The reset value of this register is 0x7D so gives a divide by 126. Free running counter Name: Free running Bit(s) R/W 31:0 R Counter value Address: base + 0x420 Function Reset: 0x000 The free running counter is not present in the SP804. The free running counter is a 32 bits wide read only register. The register is enabled by setting bit 9 of the Timer control register. The free running counter is incremented immediately after it is enabled. The timer can not be reset but when enabled, will always increment and roll-over. The free running counter is also running from the APB clock and has its own clock pre-divider controlled by bits 16-23 of the timer control register. This register will be halted too if bit 8 of the control register is set and the ARM is in Debug Halt mode. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 199 15 USB The USB core used in the Videocore is build from Synopsys IP. Details about the block can be found in DWC_otg_databook.pdf (Which can also be downloaded from https://www.synopsys.com/dw/ipdir.php?ds=dwc_usb_2_0_hs_otg ) . 15.1 Configuration A number of features of the block are specified before the block is build and thus can not be changed using software. The above mentioned document has a list of these under the chapter "Configuration Parameters". The following table list all configuration parameters mentioned in that chapter and the values which have been chosen. Feature/Parameter Selected value 0: HNP- and SRP-Capable OTG (Device and Host) 0: Non-LPM-capable core 0: Non-HSIC-capable core 2: Internal DMA 0: No 1: UTMI+ 1: Dedicated FS 0: Non-IC_USB-capable 0 : FS_USB interface 0: 8 bits 0: None 0: No 0: No Mode of Operation LPM Mode of Operation HSIC Mode of Operation Architecture Point-to-Point Application Only High-Speed PHY Interfaces USB 1.1 Full-Speed Serial Transceiver Interface USB IC_USB Transceiver Interface Default (Power on) Interface selection: FS_USB/IC_USB Data Width of the UTMI+ Interface Enable I2C Interface Enable ULPI Carkit Enable PHY Vendor Control Interface 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 200 Feature/Parameter Number of Device Mode Endpoints in Addition to Control Endpoint 0 Enable Dedicated Transmit FIFOs for Device IN Endpoints Enable descriptor based scatter/gather DMA Enable Option for Endpoint- Specific Interrupt Number of Device Mode Periodic IN Endpoints Selected value 7 1: Yes 0: No 0: No 0 Number of Device Mode IN Endpoints including Control Endpoint 8 0 Number of Device Mode Control Endpoints in Addition to Endpoint 0 Number of Host Mode Channels Is Periodic OUT Channel Support Needed in Host Mode Total Data FIFO RAM Depth Enable Dynamic FIFO Sizing Largest Rx Data FIFO Depth Largest Non-Periodic Host Tx Data FIFO Depth Largest Non-periodic Tx Data FIFO Depth Largest Host Mode Tx Periodic Data FIFO Dept Non-periodic Request Queue Depth Host Mode Periodic Request Queue Depth Device Mode IN Token Sequence Learning Queue Depth Width of Transfer Size Counters 0 8 1: Yes 4096 1: Yes 4096 1024 4096 4096 8 8 8 19 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 201 Feature/Parameter Width of Packet Counters Remove Optional Features Power-on Value of User ID Register Enable Power Optimization Is Minimum AHB Operating Frequency Less than 60 MHz Reset Style of Clocked always Blocks in RTL Instantiate Double- Synchronization Flops Enable Filter on "iddig" Signal from PHY Enable Filter on "vbus_valid" Signal from PHY Enable Filter on "a_valid" Signal from PHY Enable Filter on "b_valid" Signal from PHY Enable Filter on "session_end" Signal from PHY Direction of Endpoints Largest Device Mode Periodic Tx Data FIFO n Depth Selected value 10 0: No 0x2708A000 0: No 1: Yes 0: Asynchronous 1: Yes 1: Yes 1: Yes 1: Yes 1: Yes 1: Yes Mode is {IN and OUT} for all endpoints 768 for all endpoints (Except 0) 0=32 Largest Device Mode IN Endpoint Tx FIFOn Depth (n = 0 to 15) 1..5=512 when using dynamic FIFO sizing 6,7=768 15.2 Extra / Adapted registers. Besides the registers as specified in the documentation of Synopsys a numbe...
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