Broadcom BCM2835

All rights reserved page 179 8 fe framing error when

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Unformatted text preview: ro, read as don't care Type Reset RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 181 7 TXFE Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_ LCRH. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_ LCRH Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_ LCRH Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. Unsupported, write zero, read as don't care Unsupported, write zero, read as don't care RW 0x1 6 RXFF RW 0x0 5 TXFF RW 0x0 4 RXFE RW 0x0 3 BUSY RW 0x0 2 1 DCD DSR RW RW 0x0 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 182 0 CTS Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. RW 0x0 ILPR Register Synopsis This is the disabled IrDA register, writing to it has not effect and reading returns 0. Bit(s) Field Name 31:0 ILPR Description Reserved - write zero, read as don't care. Type Reset RW 0x0 IBRD Register Synopsis The UART_IBRD Register is the integer part of the baud rate divisor value. Bit(s) Field Name 31:16 15:0 IBRD Description Reserved - Write as 0, read as don't care The integer baud rate divisor. Type Reset RW 0x0 FBRD Register Synopsis The UART_FBRD Register is the fractional part of the baud rate divisor value. The baud rate divisor is calculated as follows: Baud rate divisor BAUDDIV = (FUARTCLK/(16 Baud rate)) where FUARTCLK is the UART reference clock frequency. The BAUDDIV is comprised of the integer value IBRD and the fractional value FBRD. NOTE: The contents of the IBRD and FBRD registers are not updated until transmission or reception of the current character is complete. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 183 Bit(s) Field Name 31:6 5:0 FBRD Description Reserved - Write as 0, read as don't care The fractional baud rate divisor. Type Reset RW 0x0 LCRH Register Synopsis The UARTLCR_ LCRH Register is the line control register. NOTE: The UART_LCRH, UART_IBRD, and UART_FBRD registers must not be changed: when the UART is enabled when completing a transmission or a reception when it has been programmed to become disabled. Bit(s) Field Name 31:8 7 SPS Description Reserved - Write as 0, read as don't care Stick parity select. 0 = stick parity is disabled 1 = either: if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. See Table 25 9. Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). RO 0x0 Type Reset 6:5 WLEN RW 0x0 4 FEN RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 184 3 STP2 Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. See Table 25...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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