Broadcom BCM2835

Asynchronous means the incoming signal is not sampled

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Unformatted text preview: lling edge detect disabled on GPIO Table 6-27 GPIO Asynchronous Falling Edge Detect Status Register 1 GPIO Pull-up/down Register (GPPUD) SYNOPSIS The GPIO Pull-up/down Register controls the actuation of the internal pull-up/down control line to ALL the GPIO pins. This register must be used in conjunction with the 2 GPPUDCLKn registers. Note that it is not possible to read back the current Pull-up/down settings and so it is the users' responsibility to `remember' which pull-up/downs are active. The reason for this is that GPIO pull-ups are maintained even in power-down mode when the core is off, when all register contents is lost. The Alternate function table also has the pull state which is applied after a power down. Bit(s) Field Name Description Type Reset 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 100 31-2 1-0 --PUD Unused PUD - GPIO Pin Pull-up/down 00 = Off disable pull-up/down 01 = Enable Pull Down control 10 = Enable Pull Up control 11 = Reserved *Use in conjunction with GPPUDCLK0/1/2 R R/W 0 0 Table 6-28 GPIO Pull-up/down Register (GPPUD) GPIO Pull-up/down Clock Registers (GPPUDCLKn) SYNOPSIS The GPIO Pull-up/down Clock Registers control the actuation of internal pull-downs on the respective GPIO pins. These registers must be used in conjunction with the GPPUD register to effect GPIO Pull-up/down changes. The following sequence of events is required: 1. Write to GPPUD to set the required control signal (i.e. Pull-up or Pull-Down or neither to remove the current Pull-up/down) 2. Wait 150 cycles this provides the required set-up time for the control signal 3. Write to GPPUDCLK0/1 to clock the control signal into the GPIO pads you wish to modify NOTE only the pads which receive a clock will be modified, all others will retain their previous state. 4. Wait 150 cycles this provides the required hold time for the control signal 5. Write to GPPUD to remove the control signal 6. Write to GPPUDCLK0/1 to remove the clock Bit(s) Field Name (31-0) PUDCLKn (n=0..31) Description 0 = No Effect 1 = Assert Clock on line (n) *Must be used in conjunction with GPPUD Type Reset R/W 0 Table 6-29 GPIO Pull-up/down Clock Register 0 Bit(s) Field Name 31-22 21-0 - Description Reserved Type Reset R R/W 0 0 PUDCLKn (n=32..53) 0 = No Effect 1 = Assert Clock on line (n) *Must be used in conjunction with GPPUD Table 6-30 GPIO Pull-up/down Clock Register 1 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 101 6.2 Alternative Function Assignments Every GPIO pin can carry an alternate function. Up to 6 alternate function are available but not every pin has that many alternate functions. The table below gives a quick over view. Pull GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 High High High High High High High High High Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low High High High Low Low Low Low ALT0 SDA0 SCL0 SDA1 SCL1 GPCLK0 GPCLK1 GPCLK2 SPI0_CE1_N SPI0_CE0_N SPI0_MISO SPI0_MOSI SPI0_SCLK PWM0 PWM1 TXD0 RXD0 <reserved> <reserved> PCM_CLK PCM_FS PCM_DIN PCM_DOUT <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> SDA0 SCL0 <reserved> <reserved> GPCLK0 <reserved> GPCLK0 SPI0_CE1_N SPI0_CE0_N SPI0_MISO SPI0_MOSI SPI0_SCLK PWM0 ALT1 SA5 SA4 SA3 SA2 SA1 SA0 SOE_N / SE SWE_N / SRW_N SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SD16 SD17 <reserved> <reserved> SA5 SA4 SA3 SA2 SA1 SA0 SOE_N / SE SWE_N / SRW_N SD0 SD1 SD2 SD3 SD4 ALT2 <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> <reserved> PCM_CLK PCM_FS PCM_DIN PCM_DOUT <reserved> <reserved> <reserved> ALT3 ALT4 ALT5 ARM_TDI ARM_TDO ARM_RTCK ARM_TMS ARM_TCK TXD1 RXD1 CTS0 RTS0 BSCSL SDA / MOSI BSCSL SCL / SCLK BSCSL / MISO BSCSL / CE_N SD1_CLK SD1_CMD SD1_DAT0 SD1_DAT1 SD1_DAT2 SD1_DAT3 <reserved> <reserved> CTS0 RTS0 TXD0 RXD0 <reserved> <reserved> CTS1 RTS1 TXD1 RXD1 SPI1_CE2_N SPI1_CE1_N SPI1_CE0_N SPI1_MISO SPI1_MOSI SPI1_SCLK ARM_TRST ARM_RTCK ARM_TDO ARM_TCK ARM_TDI ARM_TMS CTS1 RTS1 PWM0 PWM1 GPCLK0 GPCLK1 TXD0 RXD0 RTS0 CTS0 <reserved> <reserved> <reserved> <reserved> <reserved> SPI2_MISO TXD1 Pull ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 102 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 GPIO52 GPIO53 Low Low Low High High High High High High High High PWM1 GPCLK1 GPCLK2 GPCLK1 PWM1 <Internal> <Internal> <Internal> <Internal> <Internal&gt...
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