Unformatted text preview: of transmission when the CTS line becomes de-asserted will be finished. RTS auto flow control impacts the receiver only. In fact the name RTS for the control line is incorrect and should be RTR (Ready to Receive). The receiver will de-asserted the RTS (RTR) line when its receive FIFO has a number of empty spaces left. Normally 3 empty spaces should be enough. If looping back a mini UART using full auto flow control the logic is fast enough to allow the RTS auto flow level of '10' (De-assert RTS when the receive FIFO has 1 empty space left). Auto flow polarity To offer full flexibility the polarity of the CTS and RTS (RTR) lines can be programmed. This should allow the mini UART to interface with any existing hardware flow control available. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 17 AUX_MU_STAT_REG Register (0x7E21 5064)
SYNOPSIS The AUX_MU_STAT_REG provides a lot of useful information about the internal status of the mini UART not found on a normal 16550 UART. Bit(s) 31:28 27:24 Field Name Description Reserved, write zero, read as don't care Type Reset Transmit These bits shows how many symbols are stored in the R FIFO fill level transmit FIFO The value is in the range 0-8 Reserved, write zero, read as don't care Receive FIFO fill level These bits shows how many symbols are stored in the R receive FIFO The value is in the range 0-8 Reserved, write zero, read as don't care Transmitter done This bit is set if the transmitter is idle and the transmit R FIFO is empty. It is a logic AND of bits 2 and 8 R R R R R 0 23:20 19:16 0 15:10 9 1 8 7 6 5 4 Transmit If this bit is set the transmitter FIFO is empty. Thus it FIFO is empty can accept 8 symbols. CTS line RTS status Transmit FIFO is full Receiver overrun This bit shows the status of the UART1_CTS line. This bit shows the status of the UART1_RTS line. This is the inverse of bit 1 This bit is set if there was a receiver overrun. That is: one or more characters arrived whilst the receive FIFO was full. The newly arrived characters have been discarded. This bit is cleared each time the AUX_MU_LSR_REG register is read. If this bit is set the transmitter is idle. If this bit is clear the transmitter is idle. If this bit is set the receiver is idle. If this bit is clear the receiver is busy. This bit can change unless the receiver is disabled If this bit is set the mini UART transmitter FIFO can accept at least one more symbol. If this bit is clear the mini UART transmitter FIFO is full 1 0 0 0 0 3 2 Transmitter is idle Receiver is idle Space available R R 1 1 1 R 0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 18 0 Symbol available If this bit is set the mini UART receive FIFO contains R at least 1 symbol If this bit is clear the mini UART receiver FIFO is empty 0 Receiver is idle This bit is only useful if the receiver is disabled. The normal use is to disable the receiver. Then check (or wait) until the bit is set. Now you can be sure that no new symbols will arrive. (e.g. now you can change the baudrate...) Transmitter is idle This bit tells if the transmitter is idle. Note that the bit will set only for a short time if the transmit FIFO contains data. Normally you want to use bit 9: Transmitter done. RTS status This bit is useful only in receive Auto flow-control mode as it shows the status of the RTS line. AUX_MU_BAUD Register (0x7E21 5068)
SYNOPSIS The AUX_MU_BAUD register allows direct access to the 16-bit wide baudrate counter. Bit(s) 31:16 15:0 Field Name Description Reserved, write zero, read as don't care Type Reset Baudrate mini UART baudrate counter R/W 0 This is the same register as is accessed using the LABD bit and the first two register, but much easier to access. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 19 2.3 Universal SPI Master (2x) The two universal SPI masters are secondary low throughput5 SPI interfaces. Like the UART the devices needs to be enabled before they can be used. Each SPI master has the following features: Single beat bit length between 1 and 32 bits. Single beat variable bit length between 1 and 24 bits Multi beat infinite bit length. 3 independent chip selects per master. 4 entries 32-bit wide transmit and receive FIFOs. Data out on rising or falling clock edge. Data in on rising or falling clock edge. Clock inversion (Idle high or idle low). Wide clocking range. Programmable data out hold time. Shift in/out MS or LS bit first A major issue with an SPI interface is that there is no SPI standard in any form. Because the SPI interface has been around for a long time some pseudo-standard rules have appeared mostly when interfacing with memory devices. The universal SPI master has been developed to work even with the most 'non-standard' SPI devices. 2.3.1 SPI implementation details The following diagrams shows a typical SPI ac...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.
- Spring '13