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Unformatted text preview: cess cycle. In this case we have 8 SPI clocks.
1 Bit time Clk Cs_n Set-up Operate Hold
(optional) Idle One bit time before any clock edge changes the CS_n will go low. This makes sure that the MOSI signal has a full bit-time of set-up against any changing clock edges. The operation normally ends after the last clock cycle. Note that at the end there is one halfbit time where the clock does not change but which still is part of the operation cycle. There is an option to add a half bit cycle hold time. This makes sure that any MISO data has at least a full SPI bit time to arrive. (Without this hold time, data clocked out of the SPI device on the last clock edge would have only half a bit time to arrive). 5 Again the SPIs themselves have no throughput limitations in fact they can run with an SPI clock of 125 MHz. But doing so requires significant CPU involvement as they have shallow FIFOs and no DMA support. Page 20 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Last there is a guarantee of at least a full bit time where the spi chip select is high. A longer CS_n high period can be programmed for another 1-7 cycles. The SPI clock frequency is: system _ clock _ freq SPIx _ CLK = 2 * ( speed _ field + 1) If the system clock is 250 MHz and the speed field is zero the SPI clock frequency is 125 MHz. The practical SPI clock will be lower as the I/O pads can not transmit or receive signals at such high speed. The lowest SPI clock frequency with a 250 MHz system clock is 30.5 KHz. The hardware has an option to add hold time to the MOSI signal against the SPI clk. This is again done using the system clock. So a 250 MHz system clock will add hold times in units of 4 ns. Hold times of 0, 1, 4 and 7 system clock cycles can be used. (So at 250MHz an additional hold time of 0, 4, 16 and 28 ns can be achieved). The hold time is additional to the normal output timing as specified in the data sheet. 2.3.2 Interrupts The SPI block has two interrupts: TX FIFO is empty, SPI is Idle. TX FIFO is empty: This interrupt will be asserted as soon as the last entry has been read from the transmit FIFO. At that time the interface will still be busy shifting out that data. This also implies that the receive FIFO will not yet contain the last received data. It is possible at that time to fill the TX FIFO again and read the receive FIFO entries which have been received. Note that there is no "receive FIFO full" interrupt as the number of entries received is always equal to the number of entries transmitted. SPI is IDLE: This interrupt will be asserted when the transmit FIFO is empty and the SPI block has finished all actions (including the CS-high time) By this time the receive FIFO will have all received data as well. 2.3.3 Long bit streams The SPI module works in bursts of maximum 32 bits. Some SPI devices require data which is longer the 32 bits. To do this the user must make use of the two different data TX addresses: Tx data written to one address cause the CS to remain asserted. Tx data written to the other address cause the CS to be de-asserted at the end of the transmit cycle. So in order to exchange 96 bits you do the following: Write the first two data words to one address, then write the third word to the other address. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 21 2.3.4 SPI register details. AUXSPI0/1_CNTL0 Register (0x7E21 5080,0x7E21 50C0)
SYNOPSIS The AUXSPIx_CNTL0 register control many features of the SPI interfaces. Bit(s) Field Name 31:20 Speed 19:17 chip selects 16 15 post-input mode Variable CS Description Sets the SPI clock speed. spi clk freq = system_clock_freq/2*(speed+1) The pattern output on the CS pins when active. If set the SPI input works in post input mode. For details see text further down Type Reset R/W 0 R/W 111 R/W 0 If 1 the SPI takes the CS pattern and the data from the R/W 0 TX fifo If 0 the SPI takes the CS pattern from bits 17-19 of this register Set this bit only if also bit 14 (variable width) is set 14 Variable width If 1 the SPI takes the shift length and the data from R/W 0 the TX fifo If 0 the SPI takes the shift length from bits 0-5 of this register Controls the extra DOUT hold time in system clock cycles. 00 : No extra hold time 01 : 1 system clock extra hold time 10 : 4 system clocks extra hold time 11 : 7 system clocks extra hold time Enables the SPI interface. Whilst disabled the FIFOs can still be written to or read from This bit should be 1 during normal operation. If 1 data is clocked in on the rising edge of the SPI clock If 0 data is clocked in on the falling edge of the SPI clock If 1 the receive and transmit FIFOs are held in reset (and thus flushed.) This bit should be 0 during normal operation. R/W 0 13:12 DOUT Hold time 11 Enable R/W 0 10 In rising R/W 0 9 Clear FIFOs R/W 0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 22 8 Out rising If 1 data is clocked out on the rising edge of the...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.
- Spring '13