Broadcom BCM2835

Bits 318 72 1 field name description reserved write

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Unformatted text preview: ART but are ignored here Type Reset 0 R/W 0 RTS If clear the UART1_RTS line is high If set the UART1_RTS line is low This bit is ignored if the RTS is used for auto-flow control. See the Mini Uart Extra Control register description) Reserved, write zero, read as don't care This bit has a function in a 16550 compatible UART but is ignored here 0 0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 14 AUX_MU_LSR_REG Register (0x7E21 5054) SYNOPSIS The AUX_MU_LSR_REG register shows the data status. Bit(s) 31:8 7 6 5 Field Name Description Reserved, write zero, read as don't care Reserved, write zero, read as don't care This bit has a function in a 16550 compatible UART but is ignored here Type Reset 0 R R 1 0 Transmitter idle Transmitter empty This bit is set if the transmit FIFO is empty and the transmitter is idle. (Finished shifting out the last bit). This bit is set if the transmit FIFO can accept at least one byte. Reserved, write zero, read as don't care Some of these bits have functions in a 16550 compatible UART but are ignored here 4:2 1 Receiver Overrun 0 R/C 0 This bit is set if there was a receiver overrun. That is: one or more characters arrived whilst the receive FIFO was full. The newly arrived charters have been discarded. This bit is cleared each time this register is read. To do a non-destructive read of this overrun bit use the Mini Uart Extra Status register. This bit is set if the receive FIFO holds at least 1 symbol. 0 Data ready R 0 AUX_MU_MSR_REG Register (0x7E21 5058) SYNOPSIS The AUX_MU_MSR_REG register shows the 'modem' status. Bit(s) 31:8 7:6 5 Field Name Description Reserved, write zero, read as don't care Reserved, write zero, read as don't care Some of these bits have functions in a 16550 compatible UART but are ignored here Type Reset 0 1 CTS status This bit is the inverse of the UART1_CTS input Thus R : If set the UART1_CTS pin is low If clear the UART1_CTS pin is high Reserved, write zero, read as don't care Some of these bits have functions in a 16550 compatible UART but are ignored here 3:0 0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 15 AUX_MU_SCRATCH Register (0x7E21 505C) SYNOPSIS The AUX_MU_SCRATCH is a single byte storage. Bit(s) 31:8 7:0 Field Name Description Reserved, write zero, read as don't care Type Reset Scratch One whole byte extra on top of the 134217728 provided by the SDC R/W 0 AUX_MU_CNTL_REG Register (0x7E21 5060) SYNOPSIS The AUX_MU_CNTL_REG provides access to some extra useful and nice features not found on a normal 16550 UART . Bit(s) Field Name 31:8 7 CTS assert level Description Reserved, write zero, read as don't care This bit allows one to invert the CTS auto flow operation polarity. If set the CTS auto flow assert level is low* If clear the CTS auto flow assert level is high* This bit allows one to invert the RTS auto flow operation polarity. If set the RTS auto flow assert level is low* If clear the RTS auto flow assert level is high* Type Reset R/W 0 6 RTS assert level R/W 0 5:4 RTS AUTO flow level These two bits specify at what receiver FIFO level the R/W RTS line is de-asserted in auto-flow mode. 00 : De-assert RTS when the receive FIFO has 3 empty spaces left. 01 : De-assert RTS when the receive FIFO has 2 empty spaces left. 10 : De-assert RTS when the receive FIFO has 1 empty space left. 11 : De-assert RTS when the receive FIFO has 4 empty spaces left. If this bit is set the transmitter will stop if the CTS R/W line is de-asserted. If this bit is clear the transmitter will ignore the status of the CTS line 0 3 Enable transmit Auto flow-control using CTS 0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 16 2 Enable receive Auto flowcontrol using RTS If this bit is set the RTS line will de-assert if the receive FIFO reaches it 'auto flow' level. In fact the RTS line will behave as an RTR (Ready To Receive) line. If this bit is clear the RTS line is controlled by the AUX_MU_MCR_REG register bit 1. R/W 0 1 Transmitter enable Receiver enable If this bit is set the mini UART transmitter is enabled. R/W If this bit is clear the mini UART transmitter is disabled If this bit is set the mini UART receiver is enabled. If this bit is clear the mini UART receiver is disabled R/W 1 0 1 Receiver enable If this bit is set no new symbols will be accepted by the receiver. Any symbols in progress of reception will be finished. Transmitter enable If this bit is set no new symbols will be send the transmitter. Any symbols in progress of transmission will be finished. Auto flow control Automatic flow control can be enabled independent for the receiver and the transmitter. CTS auto flow control impacts the transmitter only. The transmitter will not send out new symbols when the CTS line is de-asserted. Any symbols in progress...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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