Broadcom BCM2835

Bits field name 3116 150 ibrd description reserved

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Unformatted text preview: 9. Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. See Table 25 9. Send break. If this bit is set to 1, a low-level is continually output on the TXD output, after completing transmission of the current character. RW 0x0 2 EPS RW 0x0 1 PEN RW 0x0 0 BRK RW 0x0 CR Register Synopsis The UART_CR Register is the control register. NOTE: To enable transmission, the TXE bit and UARTEN bit must be set to 1. Similarly, to enable reception, the RXE bit and UARTEN bit, must be set to 1. NOTE: Program the control registers as follows: 1. Disable the UART. 2. Wait for the end of transmission or reception of the current character. 3. Flush the transmit FIFO by setting the FEN bit to 0 in the Line Control Register, UART_LCRH. 4. Reprogram the Control Register, UART_CR. 5. Enable the UART. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 185 Bit(s) Field Name 31:16 15 CTSEN Description Reserved - Write as 0, read as don't care CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. Unsupported, write zero, read as don't care Unsupported, write zero, read as don't care Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. Unsupported, write zero, read as don't care Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for UART signals. When the UART is disabled in the middle of reception, it completes the current character before stopping. Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for UART signals. When the UART is disabled in the middle of transmission, it completes the current character before stopping. Loopback enable. If this bit is set to 1, the UARTTXD path is fed through to the UARTRXD path. In UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. Type Reset RW 0x0 14 RTSEN RW 0x0 13 12 11 OUT2 OUT1 RTS RO RO RW 0x0 0x0 0x0 10 9 DTR RXE RO RW 0x0 0x1 8 TXE RW 0x1 7 LBE RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 186 6:3 2 1 0 SIRLP SIREN UARTEN Reserved - Write as 0, read as don't care Unsupported, write zero, read as don't care Unsupported, write zero, read as don't care UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. RO RO RW 0x0 0x0 0x0 IFLS Register Synopsis The UART_IFLS Register is the interrupt FIFO level select register. You can use this register to define the FIFO level that triggers the assertion of the combined interrupt signal. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. The bits are reset so that the trigger level is when the FIFOs are at the halfway mark. Bit(s) Field Name 31:12 11:9 8:6 5:3 RXIFPSEL TXIFPSEL RXIFLSEL Description Reserved - Write as 0, read as don't care Unsupported, write zero, read as don't care Unsupported, write zero, read as don't care RO RO 0x0 0x0 0x0 Type Reset Receive interrupt FIFO level select. The RW trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes 1/8 full b001 = Receive FIFO becomes 1/4 full b010 = Receive FIFO becomes 1/2 full b011 = Receive FIFO becomes 3/4 full b100 = Receive FIFO becomes 7/8 full b101-b111 = reserved. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 187 2:0 TXIFLSEL Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes 1/8 full b001 = Transmit FIFO becomes 1/4 full b010 = Transmit FIFO becomes 1/2 full b011 = Transmit FIFO becomes 3/4 full b100 = Transmit FIFO becomes 7/8 full b101-b111 = reserved. RW 0x0 IMSC Register Synopsis The UART_IMSC Register is the interrupt mask set/clear register. It is a read/write register. On a read this register returns the current value of the mask on the relevant interrupt. On a write of 1 to the particular bit, it sets the corresponding mask of that interrupt. A write of 0 clears the corresponding mask. Bit(s) Field Name 31:11 10 OEIM Description Reserved - Write as 0, read a...
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