Broadcom BCM2835

Description reserved write as 0 read as dont care

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Unformatted text preview: divider used by the BSC. Description Reserved - Write as 0, read as don't care Type Reset Bit(s) 31:16 15:0 Field Name CDIV Clock Divider SCL = core clock / CDIV Where core_clk is nominally 150 MHz. If CDIV is set to 0, the divisor is 32768. CDIV is always rounded down to an even number. The default value should result in a 100 kHz I2C clock frequency. RW 0x5dc DEL Register Synopsis The data delay register provides fine control over the sampling/launch point of the data. The REDL field specifies the number core clocks to wait after the rising edge before sampling the incoming data. The FEDL field specifies the number core clocks to wait after the falling edge before outputting the next data bit. Note: Care must be taken in choosing values for FEDL and REDL as it is possible to cause the BSC master to malfunction by setting values of CDIV/2 or greater. Therefore the delay values should always be set to less than CDIV/2. Description FEDL Falling Edge Delay Number of core clock cycles to wait after the falling edge of SCL before outputting next bit of data. REDL Rising Edge Delay Number of core clock cycles to wait after the rising edge of SCL before reading the next bit of data. Type RW Reset 0x30 Bit(s) 31:16 Field Name FEDL 15:0 REDL RW 0x30 CLKT Register 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 34 Synopsis The clock stretch timeout register provides a timeout on how long the master waits for the slave to stretch the clock before deciding that the slave has hung. The TOUT field specifies the number I2C SCL clocks to wait after releasing SCL high and finding that the SCL is still low before deciding that the slave is not responding and moving the I2C machine forward. When a timeout occurs, the I2CS.CLKT bit is set. Writing 0x0 to TOUT will result in the Clock Stretch Timeout being disabled. Description Reserved - Write as 0, read as don't care Type Reset Bit(s) 31:16 15:0 Field Name TOUT TOUT Clock Stretch Timeout Value Number of SCL clock cycles to wait after the rising edge of SCL before deciding that the slave is not responding. RW 0x40 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 35 3.3 10 Bit Addressing 10 Bit addressing is an extension to the standard 7-bit addressing mode. This section describes in detail how to read/write using 10-bit addressing with this I2C controller. 10-bit addressing is compatible with, and can be combined with, 7 bit addressing. Using 10 bits for addressing exploits the reserved combination 1111 0xx for the first byte following a START (S) or REPEATED START (Sr) condition. The 10 bit slave address is formed from the first two bytes following a S or Sr condition. The first seven bits of the first byte are the combination 11110XX of which the last two bits (XX) are the two most significant bits of the 10-bit address. The eighth bit of the first byte is the R/W bit. If the R/W bit is `0' (write) then the following byte contains the remaining 8 bits of the 10-bit address. If the R/W bit is `1' then the next byte contains data transmitted from the slave to the master. Writing Slave acknowledge Start Stop Figure 3-1 Write to a slave with 10 bit address Figure 3-1 shows a write to a slave with a 10-bit address, to perform this using the controller one must do the following: Assuming we are in the `stop' state: (and the FIFO is empty) 1. Write the number of data bytes to written (plus one) to the I2CDLEN register. 2. Write `XXXXXXXX' to the FIFO where `XXXXXXXX' are the least 8 significant bits of the 10-bit slave address. 3. Write other data to be transmitted to the FIFO. 4. Write `11110XX' to Slave Address Register where `XX' are the two most significant bits of the 10-bit address. Set I2CC.READ = 0 and I2CC.ST = 1, this will start a write transfer. Reading Slave acknowledge Master acknowledge 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Repeat All 2012 Broadcom Corporation. Startrights reserved Page 36 Figure 3-2 Read from slave with 10 bit address Figure 3-2 shows how a read from a slave with a 10-bit address is performed. Following is the procedure for performing a read using the controller: 1. Write 1 to the I2CDLEN register. 2. Write `XXXXXXXX' to the FIFO where `XXXXXXXX' are the least 8 significant bits of the 10-bit slave address. 3. Write `11110XX' to the Slave Address Register where `XX' are the two most significant bits of the 10-bit address. Set I2CC.READ = 0 and I2CC.ST = 1, this will start a write transfer. 4. Poll the I2CS.TA bit, waiting for the transfer has started. 5. Write the number of data bytes to read to the I2CDLEN register. 6. Set I2CC.READ = 1 and I2CC.ST = 1, this will send the repeat start bit, new slave address and R/W bit (which is `1') initiating the read. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Bro...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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