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Unformatted text preview: Mini Uart Line Control Mini Uart Modem Control Mini Uart Line Status Mini Uart Modem Status Mini Uart Scratch Mini Uart Extra Control Mini Uart Extra Status Mini Uart Baudrate 8 8 8 8 8 8 32 16 32 8 32 32 16 32 8 AUX_SPI0_CNTL0_REG SPI 1 Control register 0 AUX_SPI0_CNTL1_REG SPI 1 Control register 1 AUX_SPI0_STAT_REG AUX_SPI0_IO_REG AUX_SPI0_PEEK_REG SPI 1 Status SPI 1 Data SPI 1 Peek AUX_SPI1_CNTL0_REG SPI 2 Control register 0 AUX_SPI1_CNTL1_REG SPI 2 Control register 1 These register names are identical to the defines in the AUX_IO header file. For programming purposes these names should be used wherever possible. Page 8 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved 0x7E21 50C8 AUX_SPI1_STAT_REG SPI 2 Status SPI 2 Data SPI 2 Peek 32 32 16 0x7E21 50D0 AUX_SPI1_IO_REG 0x7E21 50D4 AUX_SPI1_PEEK_REG 2.1.1 AUX registers There are two Auxiliary registers which control all three devices. One is the interrupt status register, the second is the Auxiliary enable register. The Auxiliary IRQ status register can help to hierarchically determine the source of an interrupt. AUXIRQ Register (0x7E21 5000)
SYNOPSIS The AUXIRQ register is used to check any pending interrupts which may be asserted by the three Auxiliary sub blocks. Bit(s) 31:3 2 1 0 Field Name Description Reserved, write zero, read as don't care Type Reset SPI 2 IRQ SPI 1 IRQ Mini UART IRQ If set the SPI 2 module has an interrupt pending. If set the SPI1 module has an interrupt pending. If set the mini UART has an interrupt pending. R R R 0 0 0 AUXENB Register (0x7E21 5004)
SYNOPSIS The AUXENB register is used to enable the three modules; UART, SPI1, SPI2. Bit(s) 31:3 2 Field Name Description Reserved, write zero, read as don't care Type Reset SPI2 enable If set the SPI 2 module is enabled. If clear the SPI 2 module is disabled. That also disables any SPI 2 module register access If set the SPI 1 module is enabled. If clear the SPI 1 module is disabled. That also disables any SPI 1 module register access If set the mini UART is enabled. The UART will immediately start receiving data, especially if the UART1_RX line is low. If clear the mini UART is disabled. That also disables any mini UART register access R/W 0 1 SPI 1 enable R/W 0 0 Mini UART enable R/W 0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 9 If the enable bits are clear you will have no access to a peripheral. You can not even read or write the registers! GPIO pins should be set up first the before enabling the UART. The UART core is build to emulate 16550 behaviour. So when it is enabled any data at the inputs will immediately be received . If the UART1_RX line is low (because the GPIO pins have not been set-up yet) that will be seen as a start bit and the UART will start receiving 0x00-characters. Valid stops bits are not required for the UART. (See also Implementation details). Hence any bit status is acceptable as stop bit and is only used so there is clean timing start for the next bit. Looking after a reset: the baudrate will be zero and the system clock will be 250 MHz. So only 2.5 seconds suffice to fill the receive FIFO. The result will be that the FIFO is full and overflowing in no time flat.
2.2 Mini UART The mini UART is a secondary low throughput4 UART intended to be used as a console. It needs to be enabled before it can be used. It is also recommended that the correct GPIO function mode is selected before enabling the mini Uart. The mini Uart has the following features: 7 or 8 bit operation. 1 start and 1 stop bit. No parities. Break generation. 8 symbols deep FIFOs for receive and transmit. SW controlled RTS, SW readable CTS. Auto flow control with programmable FIFO level. 16550 like registers. Baudrate derived from system clock. Break detection Framing errors detection. Parity bit Receive Time-out interrupt DCD, DSR, DTR or RI signals. This is a mini UART and it does NOT have the following capabilities: The implemented UART is not a 16650 compatible UART However as far as possible the first 8 control and status registers are laid out like a 16550 UART. Al 16550 register bits which are not supported can be written but will be ignored and read back as 0. All control bits for simple UART receive/transmit operations are available. 4 The UART itself has no throughput limitations in fact it can run up to 32 Mega baud. But doing so requires significant CPU involvement as it has shallow FIFOs and no DMA support. Page 10 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved 2.2.1 Mini UART implementation details. The UART1_CTS and UART1_RX inputs are synchronised and will take 2 system clock cycles before they are processed. The module does not check for any framing errors. After receiving a start bit and 8 (or 7) data bits the receiver wai...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.
- Spring '13