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Unformatted text preview: r of extra registers have been added. These control the Analogue USB Phy and the connections of the USB block into the Video core bus structure. Also the USB_GAHBCFG register has an alternative function for the bits [4:1].
Base Address of the USB block 0x7E98_0000 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 202 Offset Address
0x080 USB_MDIO_CNTL 0x084 USB_MDIO_GEN 0x088 USB_VBUS_DRV Description
MDIO interface control Data for MDIO interface Vbus and other Miscellaneous controls Size Read/ Write
R/W R/W R/W 32 USB MDIO Control (USB_MDIO_CNTL) Address
0x 7E98 0080
31 30-24 23 22 21 20 19:16 15:0 Field Name
mdio_busy bb_mdo bb_mdc bb_enbl freerun mdc_ratio mdi Description
1= MDIO read or write in progress 0= MDIO Idle Unused Direct write (bitbash) MDO output Direct write (bitbash) MDC output 1= MDIO bitbash enable 0= MDIO under control of the phy 1= MDC is continous active 0 = MDC only active during data transfer MDC clock freq is sysclk/mdc_ratio 16-bit read of MDIO input shift register. Updates on falling edge of MDC Read/ Reset Write
R R/W R/W R/W R/W R/W RO 0 0 0 0 0 0 0 0 Table 15-1 MDIO Control USB MDIO Data (USB_MDIO_DATA) Address
0x 7E98 0084
31-0 31-0 Field Name
mdio_data mdio_data Description
32-bit sequence to send over MDIO bus 32-bit sequence received from MDIO bus Read/ Reset Write
W R 0 0 Table 15-2 USB MDIO data A Preamble is not auto-generated so any MDIO access must be preceded by a write to this register of 0xFFFFFFFF. Furthermore, a bug in the USB PHY requires an extra clock edge so a write of 0x00000000 must follow the actual access. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 203 USB VBUS (USB_VBUS) Address
0x 7E98 0088
axi_priority vbus_irq Bit Number
31-20 19-16 15:10 9 Description
Unused Sets the USB AXI priority level Unused 1=one or more bits of [6:4] have changed since last read. This bit is cleared when the register is read. 1=Enable IRQ on VBUS status change 1=USB PHY AFE pull ups/pull downs are off 0=Normal USB AFE operation (Has no effect if MDIO mode is enabled in the phy) Drive VBUS Charge VBUS Discharge VBUS A session Valid B session Valid VBUS valid Session end Read/ Write
R/W RC Reset
0 0 0 0 8 7 vbus_irq_en afe_non_driving R/W R/W 0 0 6 5 4 3 2 1 0 utmisrp_dischrgv bus utmisrp_chrgvbu s utmiotg_drvvbus utmiotg_avalid utmiotg_bvalid utmiotg_vbusvali d utmisrp_sessend R R R R/W R/W R/W R/W 0 0 0 0 0 0 0 Table 15-3 USB MDIO data The RW bits in this register are fed into the USB2.0 controller and the RO bits are coming out of it. In the real device, it will be up to the software to communicate this information between the USB2.0 controller and external VBUS device (some of these have I2C control, others will have to interface via GPIO). USB AHB configuration (USB_GAHBCFG) Address
0x 7E98 0008 The USB_GAHBCFG register has been adapted. Bits [4:1] which are marked in the Synopsys documentation as "Burst Length/Type (HBstLen)" have been used differently.  1 = Wait for all outstanding AXI writes to complete before signalling (internally) that DMA is done. 0 = don't wait. Not used  [2:1] Sets the maximum AXI burst length, but the bits are inverted, 00 = maximum AXI burst length of 4, 01 = maximum AXI burst length of 3, 10 = maximum AXI burst length of 2 11 = maximum AXI burst length of 1 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 204 Personal Notes: 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 205...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.
- Spring '13