Broadcom BCM2835

In serial mode serialised data is transmitted within

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Unformatted text preview: efore requires tight coupling of state machines of the channels. If any of the channel range (period) value is different than the others this will cause the channels with small range values to wait between words hence resulting in gaps between words. To avoid that, each channel sharing the FIFO should be configured to use the same range value. Also note that RPTLi are not meaningful when the FIFO is shared between channels as there is no defined channel to own the last data in the FIFO. Therefore sharing channels must have their RPTLi set to zero. If the set of channels to share the FIFO has been modified after a configuration change, FIFO should be cleared before writing new data. Description Channel FIFO Input Type RW Reset 0x0 Bit(s) 31:0 Field Name PWM_FIFO RNG2 Register 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 146 Synopsis This register is used to define the range for the corresponding channel. In PWM mode evenly distributed pulses are sent within a period of length defined by this register. In serial mode serialised data is transmitted within the same period. If the value in PWM_RNGi is less than 32, only the first PWM_RNGi bits are sent resulting in a truncation. If it is larger than 32 excess zero bits are padded at the end of data. Default value for this register is 32. Note: Channels 3 and 4 are not available in B0 and corresponding Channel Range Registers are ignored. Description Channel i Range Type RW Reset 0x20 Bit(s) 31:0 Field Name PWM_RNGi DAT2 Register Synopsis This register stores the 32 bit data to be sent by the PWM Controller when USEFi is 1. In PWM mode data is sent by pulse width modulation: the value of this register defines the number of pulses which is sent within the period defined by PWM_RNGi. In serialiser mode data stored in this register is serialised and transmitted. Note: Channels 3 and 4 are not available in B0 and corresponding Channel Data Registers are ignored. Description Channel i Data Type RW Reset 0x0 Bit(s) 31:0 Field Name PWM_DATi 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 147 10 SPI 10.1 Introduction This Serial interface peripheral supports the following features: Implements a 3 wire serial protocol, variously called Serial Peripheral Interface (SPI) or Synchronous Serial Protocol (SSP). Implements a 2 wire version of SPI that uses a single wire as a bidirectional data wire instead of one for each direction as in standard SPI. Implements a LoSSI Master (Low Speed Serial Interface) Provides support for polled, interrupt or DMA operation. 10.2 SPI Master Mode 10.2.1 Standard mode In Standard SPI master mode the peripheral implements the standard 3 wire serial protocol described below. Figure 10-1 SPI Master Typical Usage 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 148 Figure 10-2 SPI Cycle Figure 10-3 Different Clock Polarity/Phase 10.2.2 Bidirectional mode In bidirectional SPI master mode the same SPI standard is implemented except that a single wire is used for the data (MIMO) instead of the two as in standard mode (MISO and MOSI). Bidirectional mode is used in a similar way to standard mode, the only difference is that before attempting to read data from the slave, you must set the read enable (SPI_REN) bit in the SPI control and status register (SPI_CS). This will turn the bus around, and when you write to the SPI_FIFO register (with junk) a read transaction will take place on the bus, and the read data will appear in the FIFO. Figure 10-4 Bidirectional SPI Master Typical Usage 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 149 10.3 LoSSI mode Figure 10-5 LoSSI mode Typical usage The LoSSI standard allows us to issue commands to peripherals and to transfer data to and from them. LoSSI commands and parameters are 8 bits long, but an extra bit is used to indicate whether the byte is a command or data. This extra bit is set high for a parameter and low for a command. The resulting 9-bit value is serialized to the output. When reading from a LoSSI peripheral the standard allows us to read bytes of data, as well as 24 and 32 bit words. Commands and parameters are issued to a LoSSI peripheral by writing the 9-bit value of the command or data into the SPI_FIFO register as you would for SPI mode. Reads are automated in that if the serial interface peripheral detects a read command being issued, it will issue the command and complete the read transaction, putting the received data into the FIFO. 10.3.1 Command write 10.3.2 Parameter write 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 150 10.3.3 Byte read commands Byte read commands ar...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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