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See text VC IRQs 0-31 GPU pend. 0 A few selected GPU IRQs Basic pend. ARM IRQs There are three interrupt pending registers. One basic pending register and two GPU pending registers. Basic pending register. The basic pending register has interrupt pending bits for the ARM specific interrupts . To speed up the interrupt processing it also has a number of selected GPU interrupts which are deemed most likely to be required in ARM drivers. Further there are two special GPU pending bits which tell if any of the two other pending registers has bits set, one bit if a GPU interrupt 0-31 is pending, a second bit if a GPU interrupt 32-63 is pending. The 'selected GPU interrupts' on the basic pending registers are NOT taken into account for these two status bits. So the two pending 0,1 status bits tell you that 'there are more interrupt which you have not seen yet'. GPU pending registers. There are two GPU pending registers with one bit per GPU interrupt source. 7.3 Fast Interrupt (FIQ). The ARM also supports a Fast Interrupt (FIQ). One interrupt sources can be selected to be connected to the ARM FIQ input. There is also one FIQ enable. An interrupt which is selected as FIQ should have its normal interrupt enable bit cleared. Otherwise an normal and a FIQ interrupt will be fired at the same time. Not a good idea! 7.4 Interrupt priority. There is no priority for any interrupt. If one interrupt is much more important then all others it can be routed to the FIQ. Any remaining interrupts have to be processed by polling the pending 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 110 registers. It is up to the ARM software to device a strategy. e.g. First start looking for specific pending bits or process them all shifting one bit at a time. As interrupt may arrive whilst this process is ongoing the usual care for any 'race-condition critical' code must be taken. The following ARM assembly code has been proven to work:
.macro get_irqnr_preamble, base, tmp ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE) .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ldr mov and \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)] @ get masked status \irqnr, #(ARM_IRQ0_BASE + 31) \tmp, \irqstat, #0x300 @ save bits 8 and 9 @ clear bits 8 and 9, and test bics \irqstat, \irqstat, #0x300 bne 1010f tst \tmp, #0x100 ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)] movne \irqnr, #(ARM_IRQ1_BASE + 31) @ Mask out the interrupts also present in PEND0 - see SW-5809 bicne \irqstat, #((1<<7) | (1<<9) | (1<<10)) bicne \irqstat, #((1<<18) | (1<<19)) bne 1010f tst \tmp, #0x200 ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)] movne \irqnr, #(ARM_IRQ2_BASE + 31) @ Mask out the interrupts also present in PEND0 - see SW-5809 bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25)) bicne \irqstat, #((1<<30)) beq 1020f 1010: @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) @ N.B. CLZ is an ARM5 instruction. sub eor clz sub \tmp, \irqstat, #1 \irqstat, \irqstat, \tmp \tmp, \irqstat \irqnr, \tmp 1020: @ EQ will be set if no irqs pending 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 111 .endm 7.5 Registers The base address for the ARM interrupt register is 0x7E00B000. Registers overview: Address offset7 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 IRQ basic pending IRQ pending 1 IRQ pending 2 FIQ control Enable IRQs 1 Enable IRQs 2 Enable Basic IRQs Disable IRQs 1 Disable IRQs 2 Disable Basic IRQs Name Notes The following is a table which lists all interrupts which can come from the peripherals which can be handled by the ARM. 7 This is the offset which needs to be added to the base address to get the full hardware address. Page 112 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved ARM peripherals interrupts table. # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IRQ 0-15 # 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IRQ 16-31 # 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 IRQ 32-47 # 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 IRQ 48-63 smi gpio_int gpio_int gpio_int gpio_int i2c_int spi_int pcm_int uart_int i2c_spi_slv_int pwa0 pwa1 Aux int The table above has many empty entries. These should not be enabled as they will interfere with the GPU operation. ARM peripherals interrupts table. 0 1 2 3 4 5 6 7 ARM Timer ARM Mailbox ARM Doorbell 0 ARM Doorbell 1 GPU0 halted (Or GPU1 halted if bit 10 of control register 1 is set) GPU1 halted Illegal access type 1 Illegal access type 0 Basic pending register.
The basic pending register shows which interrupt are pending. To speed up interrupts processing, a number of 'normal' interrupt status bits have been added to this register. This makes the 'IRQ pending base' register different from the other 'base' interrupt registers Name: IRQ pend base Bit(s)
31:21 20 Address: 0x200 Reset: 0x000...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.
- Spring '13