Broadcom BCM2835

Note the same behaviour is achieved from the host

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Unformatted text preview: Broadcom Corporation. All rights reserved Page 166 5:3 RXIFLSEL RXIFLSEL RX Interrupt FIFO Level Select Interrupt is triggered when : 000 RX FIFO gets 1/8 full 001 RX FIFO gets 1/4 full 010 RX FIFO gets 1/2 full 011 RX FIFO gets 3/4 full 100 RX FIFO gets 7/8 full 101 111 not used TXIFLSEL TX Interrupt FIFO Level Select Interrupt is triggered when : 000 TX FIFO gets 1/8 full 001 TX FIFO gets 1/4 full 010 TX FIFO gets 1/2 full 011 TX FIFO gets 3/4 full 100 TX FIFO gets 7/8 full 101 111 not used RW 0x0 2:0 TXIFLSEL RW 0x0 IMSC Register Synopsis Interrupt Mask Set/Clear Register. On a read this register returns the current value of the mask on the relevant interrupt. On a write of 1 to the particular bit, it sets the corresponding mask of that interrupt. A write of 0 clears the corresponding mask. Description Reserved - Write as 0, read as don't care OEIM Overrun error interrupt mask. A read returns the current mask for the interrupt. On a write of 1, the mask of the OEINTR interrupt is set. A write of 0 clears the mask. Break error interrupt mask. A read returns the current mask for the BEINTR interrupt. On a write of 1, the mask of the interrupt is set. A write of 0 clears the mask. Transmit interrupt mask. A read returns the current mask for the TXINTR interrupt. On a write of 1, the mask of the interrupt is set. A write of 0 clears the mask. Receive interrupt mask. A read returns the current mask for the RXINTR interrupt. On a write of 1, the mask of the interrupt is set. A write of 0 clears the mask. RW 0x0 Type Reset Bit(s) 31:4 3 Field Name 2 BEIM RW 0x0 1 TXIM RW 0x0 0 RXIM RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 167 RIS Register Synopsis The Raw Interrupt Status Register returns the current raw status value, prior to masking, of the corresponding interrupt. Description Reserved - Write as 0, read as don't care OERIS Overrun error interrupt status. Returns the raw interrupt state of the OEINTR interrupt. Break error interrupt status. Returns the raw interrupt state of the BEINTR interrupt. Transmit interrupt status. Returns the raw interrupt state of the TXINTR interrupt. Receive interrupt status. Returns the raw interrupt state of the RXINTR interrupt. RW 0x0 Type Reset Bit(s) 31:4 3 Field Name 2 BERIS RW 0x0 1 TXRIS RW 0x0 0 RXRIS RW 0x0 MIS Register Synopsis The Masked Interrupt Status Register returns the current masked status value of the corresponding interrupt. Description Reserved - Write as 0, read as don't care OEMIS Overrun error masked interrupt status. Returns the masked interrupt state of the OEINTR interrupt. Break error masked interrupt status. Returns the masked interrupt state of the BEINTR interrupt. Transmit masked interrupt status. Returns the masked interrupt state of the TXINTR interrupt. Receive masked interrupt status. Returns the masked interrupt state of the RXINTR interrupt. RW 0x0 Type Reset Bit(s) 31:4 3 Field Name 2 BEMIS RW 0x0 1 TXMIS RW 0x0 0 RXMIS RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 168 ICR Register Synopsis Bit(s) 31:4 3 OEIC The Interrupt Clear Register. Description Reserved - Write as 0, read as don't care Overrun error interrupt clear. Clears the OEINTR interrupt. Break error interrupt clear. Clears the BEINTR interrupt. Transmit interrupt clear. Clears the TXINTR interrupt. Receive masked interrupt status. Returns the masked interrupt state of the RXINTR interrupt. RW 0x0 Type Reset Field Name 2 BEIC RW 0x0 1 TXIC RW 0x0 0 RXIC RW 0x0 DMACR Register Synopsis Bit(s) 31:3 2 1 0 DMAONERR TXDMAE RXDMAE The DMA Control register is not supported in this version. Description Reserved - Write as 0, read as don't care Unsupported, write zero, read as don't care Unsupported, write zero, read as don't care Unsupported, write zero, read as don't care RW RW RW 0x0 0x0 0x0 Type Reset Field Name TDR Register Synopsis The Test Data Register enables data to be written into the receive FIFO and read out from the transmit FIFO for test purposes. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 169 Bit(s) 31:8 7:0 Field Name Description Reserved - Write as 0, read as don't care Type Reset DATA Test data is written into the receive FIFO and read out of the transmit FIFO. RW 0x0 GPUSTAT Register Synopsis The GPU SW Status Register to be passed via I2C bus to a Host. NOTE: GPU SW Status Register is combined with the status bit coming from within I2C SPI Slave device. Hence, the I2C SPI GPU Host Status Register as it is seen by a Host is depicted on Table 1 14. Description Reserved - Write as 0, read as don't care DATA GPUSTAT GPU to Host Status Register SW controllable RW 0x0 Type Reset Bit(s) 31:4 3:0 Field Name HCTRL Register Synopsis The Host Control register is received from the host side via I2C bus. When ENCTRL enabl...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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