Broadcom BCM2835

Reading this register will return the address of the

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Unformatted text preview: efficient access mode, so the default is to use the bursts. Add Wait Cycles This slows down the DMA throughput by setting the number of dummy cycles burnt after each DMA read or write operation is completed. A value of 0 means that no wait cycles are to be added. Peripheral Mapping Indicates the peripheral number (1-31) whose ready signal shall be used to control the rate of the transfers, and whose panic signals will be output on the DMA AXI bus. Set to 0 for a continuous un-paced transfer. Burst Transfer Length Indicates the burst length of the DMA transfers. The DMA will attempt to transfer data as bursts of this number of words. A value of zero will produce a single transfer. Bursts are only produced for specific conditions, see main text. Ignore Reads 1 = Do not perform source reads. In addition, destination writes will zero all the write strobes. This is used for fast cache fill operations. 0 = Perform source reads.. Control Source Reads with DREQ 1 = The DREQ selected by PER_MAP will gate the source reads. 0 = DREQ has no effect. Source Transfer Width 1 = Use 128-bit source read width. 0 = Use 32-bit source read width. Source Address Increment 1 = Source address increments after each read. The address will increment by 4, if S_WIDTH=0 else by 32. 0 = Source address does not change. RW 0x0 25:21 WAITS RW 0x0 20:16 PERMAP RW 0x0 15:12 BURST_LENGTH RW 0x0 11 SRC_IGNORE RW 0x0 10 SRC_DREQ RW 0x0 9 SRC_WIDTH RW 0x0 8 SRC_INC RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 51 7 DEST_IGNORE Ignore Writes 1 = Do not perform destination writes. 0 = Write data to destination. Control Destination Writes with DREQ 1 = The DREQ selected by PERMAP will gate the destination writes. 0 = DREQ has no effect. Destination Transfer Width 1 = Use 128-bit destination write width. 0 = Use 32-bit destination write width. Destination Address Increment 1 = Destination address increments after each write The address will increment by 4, if DEST_WIDTH=0 else by 32. 0 = Destination address does not change. Wait for a Write Response When set this makes the DMA wait until it receives the AXI write response for each write. This ensures that multiple writes cannot get stacked in the AXI bus pipeline. 1= Wait for the write response to be received before proceeding. 0 = Don t wait; continue as soon as the write data is sent. Reserved - Write as 0, read as don't care RW 0x0 6 DEST_DREQ RW 0x0 5 DEST_WIDTH RW 0x0 4 DEST_INC RW 0x0 3 WAIT_RESP RW 0x0 2 1 TDMODE 2D Mode 1 = 2D mode interpret the TXFR_LEN register as YLENGTH number of transfers each of XLENGTH, and add the strides to the address after each transfer. 0 = Linear mode interpret the TXFR register as a single transfer of total length {YLENGTH ,XLENGTH}. Interrupt Enable 1 = Generate an interrupt when the transfer described by the current Control Block completes. 0 = Do not generate an interrupt. RW 0x0 0 INTEN RW 0x0 0_SOURCE_AD 1_SOURCE_AD 2_SOURCE_AD 3_SOURCE_AD 4_SOURCE_AD 5_SOURCE_AD 6_SOURCE_AD 7_SOURCE_AD 8_SOURCE_AD 9_SOURCE_AD 10_SOURCE_AD 11_SOURCE_AD 12_SOURCE_AD 13_SOURCE_AD 14_SOURCE_AD Register 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 52 Synopsis DMA Source Address Description DMA Source Address Source address for the DMA operation. Updated by the DMA engine as the transfer progresses. Type Reset RW 0x0 Bit(s) Field Name 31:0 S_ADDR 0_DEST_AD 1_DEST_AD 2_DEST_AD 3_DEST_AD 4_DEST_AD 5_DEST_AD 6_DEST_AD 7_DEST_AD 8_DEST_AD 9_DEST_AD 10_DEST_AD 11_DEST_AD 12_DEST_AD 13_DEST_AD 14_DEST_AD Register Synopsis DMA Destination Address Description DMA Destination Address Destination address for the DMA operation. Updated by the DMA engine as the transfer progresses. Type Reset RW 0x0 Bit(s) Field Name 31:0 D_ADDR 0_TXFR_LEN 1_TXFR_LEN 2_TXFR_LEN 3_TXFR_LEN 4_TXFR_LEN 5_TXFR_LEN 6_TXFR_LEN Register Synopsis DMA Transfer Length. This specifies the amount of data to be transferred in bytes. In normal (non 2D) mode this specifies the amount of bytes to be transferred. In 2D mode it is interpreted as an X and a Y length, and the DMA will perform Y transfers, each of length X bytes and add the strides onto the addresses after each X leg of the transfer. The length register is updated by the DMA engine as the transfer progresses, so it will indicate the data left to transfer. Description Reserved - Write as 0, read as don't care YLENGTH When in 2D mode, This is the Y transfer length, indicating how many xlength transfers are performed. When in normal linear mode this becomes the top bits of the XLENGTH Transfer Length in bytes. RW 0x0 Type Reset Bit(s) 31:30 29:16 Field Name 15:0 XLENGTH RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 53 0_STRIDE 1_STRIDE 2_STRIDE 3_STRIDE 4_STRIDE 5_STRIDE 6_STRIDE Register Synopsis Bit(s) 31:16 DMA 2D Stride Description Destination Stride (2D Mode) Signed (2 s complement) byt...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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