Broadcom BCM2835

Returns the masked interrupt state of the beintr

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: e control register bit is set, the host control register is received as the first data character after the I2C address. Description Reserved - Write as 0, read as don't care DATA HCTRL Host Control Register SW processing received via I2C bus RW 0x0 Type Reset Bit(s) 31:8 7:0 Field Name DEBUG1 Register Synopsis I2C Debug Register 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 170 Bit(s) 31:26 25:0 Field Name Description Reserved - Write as 0, read as don't care Type Reset DATA RW 0xe DEBUG2 Register Synopsis Bit(s) 31:24 23:0 DATA SPI Debug Register Description Reserved - Write as 0, read as don't care RW 0x400000 Type Reset Field Name 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 171 REFERENCE: C6357-M-1398 BROADCOM PROPRIETARY AND CONFIDENTIAL PAGE 172 12 System Timer The System Timer peripheral provides four 32-bit timer channels and a single 64-bit free running counter. Each channel has an output compare register, which is compared against the 32 least significant bits of the free running counter values. When the two values match, the system timer peripheral generates a signal to indicate a match for the appropriate channel. The match signal is then fed into the interrupt controller. The interrupt service routine then reads the output compare register and adds the appropriate offset for the next timer tick. The free running counter is driven by the timer clock and stopped whenever the processor is stopped in debug mode. The Physical (hardware) base address for the system timers is 0x7E003000. 12.1 System Timer Registers ST Address Map Address Offset 0x0 0x4 0x8 0xc 0x10 0x14 0x18 Register Name Description Size CS CLO CHI C0 C1 C2 C3 System Timer Control/Status System Timer Counter Lower 32 bits System Timer Counter Higher 32 bits System Timer Compare 0 System Timer Compare 1 System Timer Compare 2 System Timer Compare 3 32 32 32 32 32 32 32 CS Register Synopsis System Timer Control / Status. This register is used to record and clear timer channel comparator matches. The system timer match bits are routed to the interrupt controller where they can generate an interrupt. The M0-3 fields contain the free-running counter match status. Write a one to the relevant bit to clear the match detect status bit and the corresponding interrupt request line. 2012 Broadcom Corporation. All rights reserved Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Bit(s) Field Name 31:4 3 M3 Description Reserved - Write as 0, read as don't care System Timer Match 3 0 = No Timer 3 match since last cleared. 1 = Timer 3 match detected. System Timer Match 2 0 = No Timer 2 match since last cleared. 1 = Timer 2 match detected. System Timer Match 1 0 = No Timer 1 match since last cleared. 1 = Timer 1 match detected. System Timer Match 0 0 = No Timer 0 match since last cleared. 1 = Timer 0 match detected. Type Reset RW 0x0 2 M2 RW 0x0 1 M1 RW 0x0 0 M0 RW 0x0 CLO Register Synopsis System Timer Counter Lower bits. The system timer free-running counter lower register is a read-only register that returns the current value of the lower 32-bits of the free running counter. Description Lower 32-bits of the free running counter value. Type Reset RW 0x0 Bit(s) Field Name 31:0 CNT CHI Register Synopsis System Timer Counter Higher bits. The system timer free-running counter higher register is a read-only register that returns the current value of the higher 32-bits of the free running counter. Description Higher 32-bits of the free running counter value. Type Reset RW 0x0 Bit(s) Field Name 31:0 CNT 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 173 C0 C1 C2 C3 Register Synopsis System Timer Compare. The system timer compare registers hold the compare value for each of the four timer channels. Whenever the lower 32-bits of the free-running counter matches one of the compare values the corresponding bit in the system timer control/status register is set. Each timer peripheral (minirun and run) has a set of four compare registers. Description Compare value for match channel n. Type Reset RW 0x0 Bit(s) Field Name 31:0 CMP 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 174 13 UART The BCM2835 device has two UARTS. On mini UART and and PL011 UART. This section describes the PL011 UART. For details of the mini UART see 2.2 Mini UART. The PL011 UART is a Universal Asynchronous Receiver/Transmitter. This is the ARM UART (PL011) implementation. The UART performs serial-to-parallel conversion on data characters received from an external peripheral device or modem, and parallel-to-serial conversion on data characters received from the Advanced Peripheral Bus (APB). The ARM PL011 UART has some optional functionality which can be included or left out. The following functionality is not supported : Infrared Data Asso...
View Full Document

Ask a homework question - tutors are online