Broadcom BCM2835

Select 38 fsel37 function select 37 fsel36 function

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Unformatted text preview: FSEL53 - Function Select 53 000 = GPIO Pin 53 is an input 001 = GPIO Pin 53 is an output 100 = GPIO Pin 53 takes alternate function 0 101 = GPIO Pin 53 takes alternate function 1 110 = GPIO Pin 53 takes alternate function 2 111 = GPIO Pin 53 takes alternate function 3 011 = GPIO Pin 53 takes alternate function 4 010 = GPIO Pin 53 takes alternate function 5 FSEL52 - Function Select 52 FSEL51 - Function Select 51 FSEL50 - Function Select 50 Type R R/W Reset 0 0 8-6 5-3 2-0 FSEL52 FSEL51 FSEL50 R/W R/W R/W 0 0 0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 94 Table 6-7 GPIO Alternate function select register 5 GPIO Pin Output Set Registers (GPSETn) SYNOPSIS The output set registers are used to set a GPIO pin. The SET{n} field defines the respective GPIO pin to set, writing a "0" to the field has no effect. If the GPIO pin is being used as in input (by default) then the value in the SET{n} field is ignored. However, if the pin is subsequently defined as an output then the bit will be set according to the last set/clear operation. Separating the set and clear functions removes the need for read-modify-write operations Bit(s) Field Name 31-0 SETn (n=0..31) Description 0 = No effect 1 = Set GPIO pin n Type R/W Reset 0 Table 6-8 GPIO Output Set Register 0 Bit(s) Field Name 31-22 21-0 SETn (n=32..53) Description Reserved 0 = No effect 1 = Set GPIO pin n. Type R R/W Reset 0 0 Table 6-9 GPIO Output Set Register 1 GPIO Pin Output Clear Registers (GPCLRn) SYNOPSIS The output clear registers) are used to clear a GPIO pin. The CLR{n} field defines the respective GPIO pin to clear, writing a "0" to the field has no effect. If the GPIO pin is being used as in input (by default) then the value in the CLR{n} field is ignored. However, if the pin is subsequently defined as an output then the bit will be set according to the last set/clear operation. Separating the set and clear functions removes the need for read-modify-write operations. Bit(s) Field Name 31-0 CLRn (n=0..31) Description 0 = No effect 1 = Clear GPIO pin n Type R/W Reset 0 Table 6-10 GPIO Output Clear Register 0 Bit(s) Field Name 31-22 - Description Reserved Type R Reset 0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 95 21-0 CLRn (n=32..53) 0 = No effect 1 = Set GPIO pin n R/W 0 Table 6-11 GPIO Output Clear Register 1 GPIO Pin Level Registers (GPLEVn) SYNOPSIS The pin level registers return the actual value of the pin. The LEV{n} field gives the value of the respective GPIO pin. Bit(s) Field Name 31-0 LEVn (n=0..31) Description 0 = GPIO pin n is low 0 = GPIO pin n is high Type R/W Reset 0 Table 6-12 GPIO Level Register 0 Bit(s) Field Name 31-22 21-0 - Description Reserved 0 = GPIO pin n is high Type R R/W Reset 0 0 LEVn (n=32..53) 0 = GPIO pin n is low Table 6-13 GPIO Level Register 1 GPIO Event Detect Status Registers (GPEDSn) SYNOPSIS The event detect status registers are used to record level and edge events on the GPIO pins. The relevant bit in the event detect status registers is set whenever: 1) an edge is detected that matches the type of edge programmed in the rising/falling edge detect enable registers, or 2) a level is detected that matches the type of level programmed in the high/low level detect enable registers. The bit is cleared by writing a "1" to the relevant bit. The interrupt controller can be programmed to interrupt the processor when any of the status bits are set. The GPIO peripheral has three dedicated interrupt lines. Each GPIO bank can generate an independent interrupt. The third line generates a single interrupt whenever any bit is set. Bit(s) Field Name 31-0 Description 1 = Event detected on GPIO pin n Type R/W Reset 0 EDSn (n=0..31) 0 = Event not detected on GPIO pin n Table 6-14 GPIO Event Detect Status Register 0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 96 Bit(s) Field Name 31-22 21-0 EDSn (n=32..53) Description Reserved 0 = Event not detected on GPIO pin n 1 = Event detected on GPIO pin n Type R R/W Reset 0 0 Table 6-15 GPIO Event Detect Status Register 1 GPIO Rising Edge Detect Enable Registers (GPRENn) SYNOPSIS The rising edge detect enable registers define the pins for which a rising edge transition sets a bit in the event detect status registers (GPEDSn). When the relevant bits are set in both the GPRENn and GPFENn registers, any transition (1 to 0 and 0 to 1) will set a bit in the GPEDSn registers. The GPRENn registers use synchronous edge detection. This means the input signal is sampled using the system clock and then it is looking for a "011" pattern on the sampled signal. This has the effect of suppressing glitches. Bit(s) Field Name 31-0 RENn (n=0..31) Description 0 = Rising edge detect disabled on GPIO pin n. 1 = Rising edge on GPIO pin n sets corresponding bit in EDSn. Type R/W Reset...
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