Broadcom BCM2835

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Unformatted text preview: don't care TXUE TX Underrun Error 0 - No error case detected 1 Set when TX FIFO is empty and I2C master attempt to read a data character from I2C slave. Cleared by writing 0 to it. RXOE RX Overrun Error 0 No error case detected 1 Set when RX FIFO is full and a new data character is received. Cleared by writing 0 to it. RO RW 0x0 0x0 0 OE RW 0x0 SLV Register Synopsis The I2C SPI Address Register holds the I2C slave address value. NOTE: It is of no use in SPI mode. Description Reserved - Write as 0, read as don't care ADDR SLVADDR I2C Slave Address Programmable I2C slave address Note: In case HOSTCTRLEN bit is set from the I2C SPI Control Register bit SLVADDR[0] chooses the following: 0 - selects normal operation, i.e. accessing RX and TX FIFOs. 1 - selects access to I2C SPI SW Status Register or I2C SPI Host Control Register RW 0x0 Type Reset Bit(s) 31:7 6:0 Field Name CR Register Synopsis Bit(s) 31:14 The Control register is used to configure the I2C or SPI operation. Description Reserved - Write as 0, read as don't care Type Reset Field Name 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 163 13 INV_TXF INV-RX Inverse TX status flags 0 = default status flags When this bit is 0, bit 6 (TXFE - TX FIFO Empty) will reset to a 1 1 = inverted status flags When this bit is set, bit 6 (TXFE - TX FIFO Full) will reset to a 0 * Note: INV_TX bit changes the default values of 6 bit as it is specified for I2C SPI GPU Host Status Register . RW 0x0 12 HOSTCTRLEN HOSTCTRLEN Enable Control for Host 0 = Host Control disabled 1 = Host Control enabled Note: HOSTCTRLEN allows Host to request GPUSTAT or HCTRL register. The same behaviour is achieved from the GPU side using ENSTAT and ENCTRL. TESTFIFO TEST FIFO 0 = TESTT FIFO disabled 1 = TESTT FIFO enabled INV-RX Inverse RX status flags 0 = default status flags When this bit is 0, bit 6 (RXFF - RX FIFO Full) will reset to a 0 1 = inverted status flags When this bit is 0, bit 6 (RXFF - RX FIFO Empty) will reset to a 1 * NOTE: INV_RX bit changes the default values of 7 bit as it is specified for I2C SPI GPU Host Status Register . RW 0x0 11 TESTFIFO RW 0x0 10 INV_RXF RW 0x0 9 RXE RXE Receive Enable 0 = Receive mode disabled 1 = Receive mode enabled TXE Transmit Enable 0 = Transmit mode disabled 1 = Transmit mode enabled BRK Break current operation 0 = No effect. 1 = Stop operation and clear the FIFOs. RW 0x0 8 TXE RW 0x0 7 BRK RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 164 6 ENCTRL ENCTRL ENABLE CONTROL 8bit register 0 = Control register disabled. Implies ordinary I2C protocol. 1 = Control register enabled. When enabled the control register is received as a first data character on the I2C bus. NOTE: The same behaviour is achieved from the Host side by using bit SLVADDR[6] of the slave address. ENSTAT ENABLE STATUS 8bit register 0 = Status register disabled. Implies ordinary I2C protocol. 1 = Status register enabled. When enabled the status register is transferred as a first data character on the I2C bus. Status register is transferred to the host. NOTE: The same behaviour is achieved from the Host side by using bit SLVADDR[6] of the slave address. CPOL Clock Polarity 0= 1 = SPI Related CPHA Clock Phase 0= 1 = SPI Related SPI Mode 0 = Disabled I2C mode 1 = Enabled I2C mode SPI Mode 0 = Disabled SPI mode 1 = Enabled SPI mode EN Enable Device 1 = Enable I2C SPI Slave. 0 = Disable I2C SPI Slave. RO 0x0 5 ENSTAT RW 0x0 4 CPOL RW 0x0 3 CPHA RW 0x0 2 I2C RW 0x0 1 SPI RW 0x0 0 EN RW 0x0 FR Register Synopsis Bit(s) 31:16 The flag register indicates the current status of the operation. Description Reserved - Write as 0, read as don't care Type Reset Field Name 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 165 15:11 RXFLEVEL RXFLEVEL RX FIFO Level Returns the current level of the RX FIFO use TXFLEVEL TX FIFO Level Returns the current level of the TX FIFO use RXBUSY Receive Busy 0 Receive operation inactive 1 Receive operation in operation TXFE TX FIFO Empty 0 TX FIFO is not empty 1 When TX FIFO is empty RXFE RX FIFO Full 0 FX FIFO is not full 1 When FX FIFO is full TXFF TX FIFO Full 0 TX FIFO is not full 1 When TX FIFO is full RXFE RX FIFO Empty 0 FX FIFO is not empty 1 When FX FIFO is empty TXBUSY Transmit Busy 0 Transmit operation inactive 1 Transmit operation in operation RW 0x0 10:6 TXFLEVEL RW 0x0 5 RXBUSY RW 0x0 4 TXFE RW 0x1 3 RXFF RW 0x0 2 TXFF RW 0x0 1 RXFE RW 0x1 0 TXBUSY RW 0x0 IFLS Register Synopsis Bit(s) 31:12 11:9 8:6 RXIFPSEL TXIFPSEL The flag register indicates the current status of the operation. Description Reserved - Write as 0, read as don't care Unsupported, write zero, read as don't care Unsupported, write zero, read as don't care RO RO 0x0 0x0 Type Reset Field Name 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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