Broadcom BCM2835

The mash can be programmed for 1 2 or 3 stage

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Unformatted text preview: 16.67 14.29 ave freq (MHz) 18.57 18.32 18.32 18.32 19.05 18.32 18.32 18.32 20.00 18.32 18.32 18.32 max freq (MHz) 18.57 18.57 19.12 20.31 19.05 19.05 20.00 22.22 20.00 20.00 22.22 28.57 error ok ok ok ok ok ok ok ok ok ok ok error Table 6-33 Example of Frequency Spread when using MASH Filtering It is beyond the scope of this specification to describe the operation of a MASH filter or to determine under what conditions the available levels of filtering are beneficial. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 105 Operating Frequency The maximum operating frequency of the General Purpose clocks is ~125MHz at 1.2V but this will be reduced if the GPIO pins are heavily loaded or have a capacitive load. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 106 Register Definitions Clock Manager General Purpose Clocks Control (CM_GP0CTL, GP1CTL & GP2CTL) Address 0x 7e10 1070 CM_GP0CTL 0x 7e10 1078 CM_GP1CTL 0x 7e10 1080 CM_GP2CTL Field Name PASSWD MASH Bit Number 31-24 23-11 10-9 Description Clock Manager password "5a" Unused MASH control 0 = integer division 1 = 1-stage MASH (equivalent to non-MASH dividers) 2 = 2-stage MASH 3 = 3-stage MASH To avoid lock-ups and glitches do not change this control while BUSY=1 and do not change this control at the same time as asserting ENAB. Read/ Reset Write W R R/W 0 0 0 8 FLIP Invert the clock generator output This is intended for use in test/debug only. Switching this control will generate an edge on the clock generator output. To avoid output glitches do not switch this control while BUSY=1. R/W 0 7 BUSY Clock generator is running Indicates the clock generator is running. To avoid glitches and lock-ups, clock sources and setups must not be changed while this flag is set. R 0 6 5 KILL Unused Kill the clock generator 0 = no action 1 = stop and reset the clock generator This is intended for test/debug only. Using this control may cause a glitch on the clock generator output. Enable the clock generator This requests the clock to start or stop without glitches. The output clock will not stop immediately because the cycle must be allowed to complete to avoid glitches. The BUSY flag will go low when the final cycle is completed. Clock source 0 = GND 1 = oscillator 2 = testdebug0 3 = testdebug1 4 = PLLA per 5 = PLLC per 6 = PLLD per 7 = HDMI auxiliary 8-15 = GND To avoid lock-ups and glitches do not change this control while BUSY=1 and do not change this control at the same time as asserting ENAB. R R/W 0 0 4 ENAB R/W 0 3-0 SRC R/W 0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 107 Table 6-34 General Purpose Clocks Control Clock Manager General Purpose Clock Divisors (CM_GP0DIV, CM_GP1DIV & CM_GP2DIV) Address 0x 7e10 1074 CM_GP0DIV 0x 7e10 107c CM_GP1DIV 0x 7e10 1084 CM_GP2DIV Field Name PASSWD DIVI Bit Number 31-24 23-12 Description Clock Manager password "5a" Integer part of divisor This value has a minimum limit determined by the MASH setting. See text for details. To avoid lock-ups and glitches do not change this control while BUSY=1. Fractional part of divisor To avoid lock-ups and glitches do not change this control while BUSY=1. Read/ Reset Write W R/W 0 0 11-0 DIVF R/W 0 Table 6-35 General Purpose Clock Divisors 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 108 7 Interrupts 7.1 Introduction 1. Interrupts coming from the GPU peripherals. 2. Interrupts coming from local ARM control peripherals. The ARM processor gets three types of interrupts: 1. Interrupts from ARM specific peripherals. 2. Interrupts from GPU peripherals. 3. Special events interrupts. The ARM specific interrupts are: One timer. One Mailbox. Two Doorbells. Two GPU halted interrupts. Two Address/access error interrupt The Mailbox and Doorbell registers are not for general usage. The ARM has two types of interrupt sources: For each interrupt source (ARM or GPU) there is an interrupt enable bit (read/write) and an interrupt pending bit (Read Only). All interrupts generated by the arm control block are level sensitive interrupts. Thus all interrupts remain asserted until disabled or the interrupt source is cleared. Default the interrupts from doorbell 0,1 and mailbox 0 go to the ARM this means that these resources should be written by the GPU and read by the ARM. The opposite holds for doorbells 2, 3 and mailbox 1. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 109 7.2 Interrupt pending. An interrupt vector module has NOT been implemented. To still have adequate interrupt processing the interrupt pending bits are organized as follows: GPU IRQs 32-63 GPU pe...
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