Broadcom BCM2835

Broadcom BCM2835

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Unformatted text preview: 0 Table 6-16 GPIO Rising Edge Detect Status Register 0 Bit(s) Field Name 31-22 21-0 RENn (n=32..53) Description Reserved 0 = Rising edge detect disabled on GPIO pin n. 1 = Rising edge on GPIO pin n sets corresponding bit in EDSn. Type R R/W Reset 0 0 Table 6-17 GPIO Rising Edge Detect Status Register 1 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 97 GPIO Falling Edge Detect Enable Registers (GPRENn) SYNOPSIS The falling edge detect enable registers define the pins for which a falling edge transition sets a bit in the event detect status registers (GPEDSn). When the relevant bits are set in both the GPRENn and GPFENn registers, any transition (1 to 0 and 0 to 1) will set a bit in the GPEDSn registers. The GPFENn registers use synchronous edge detection. This means the input signal is sampled using the system clock and then it is looking for a "100" pattern on the sampled signal. This has the effect of suppressing glitches. Bit(s) Field Name 31-0 FENn (n=0..31) Description 0 = Falling edge detect disabled on GPIO pin n. 1 = Falling edge on GPIO pin n sets corresponding bit in EDSn. Type Reset R/W 0 Table 6-18 GPIO Falling Edge Detect Status Register 0 Bit(s) Field Name 31-22 21-0 FENn (n=32..53) Description Reserved 0 = Falling edge detect disabled on GPIO pin n. 1 = Falling edge on GPIO pin n sets corresponding bit in EDSn. Type Reset R R/W 0 0 Table 6-19 GPIO Falling Edge Detect Status Register 1 GPIO High Detect Enable Registers (GPHENn) SYNOPSIS The high level detect enable registers define the pins for which a high level sets a bit in the event detect status register (GPEDSn). If the pin is still high when an attempt is made to clear the status bit in GPEDSn then the status bit will remain set. Bit(s) Field Name 31-0 HENn (n=0..31) Description 0 = High detect disabled on GPIO pin n 1 = High on GPIO pin n sets corresponding bit in GPEDS Type Reset R/W 0 Table 6-20 GPIO High Detect Status Register 0 Bit(s) Field Name 31-22 21-0 HENn (n=32..53) Description Reserved 0 = High detect disabled on GPIO pin n 1 = High on GPIO pin n sets corresponding bit in GPEDS Type Reset R R/W 0 0 Table 6-21 GPIO High Detect Status Register 1 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 98 GPIO Low Detect Enable Registers (GPLENn) SYNOPSIS The low level detect enable registers define the pins for which a low level sets a bit in the event detect status register (GPEDSn). If the pin is still low when an attempt is made to clear the status bit in GPEDSn then the status bit will remain set. Bit(s) Field Name 31-0 LENn (n=0..31) Description 0 = Low detect disabled on GPIO pin n 1 = Low on GPIO pin n sets corresponding bit in GPEDS Type Reset R/W 0 Table 6-22 GPIO Low Detect Status Register 0 Bit(s) Field Name 31-22 21-0 LENn (n=32..53) Description Reserved 0 = Low detect disabled on GPIO pin n 1 = Low on GPIO pin n sets corresponding bit in GPEDS Type Reset R R/W 0 0 Table 6-23 GPIO Low Detect Status Register 1 GPIO Asynchronous rising Edge Detect Enable Registers (GPARENn) SYNOPSIS The asynchronous rising edge detect enable registers define the pins for which a asynchronous rising edge transition sets a bit in the event detect status registers (GPEDSn). Asynchronous means the incoming signal is not sampled by the system clock. As such rising edges of very short duration can be detected. Bit(s) Field Name 31-0 ARENn (n=0..31) Description 0 = Asynchronous rising edge detect disabled on GPIO pin n. 1 = Asynchronous rising edge on GPIO pin n sets corresponding bit in EDSn. Type Reset R/W 0 Table 6-24 GPIO Asynchronous rising Edge Detect Status Register 0 Bit(s) Field Name 31-22 21-0 ARENn (n=32..53) Description Reserved 0 = Asynchronous rising edge detect disabled on GPIO pin n. 1 = Asynchronous rising edge on GPIO pin n sets corresponding bit in EDSn. Type Reset R R/W 0 0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 99 Table 6-25 GPIO Asynchronous rising Edge Detect Status Register 1 GPIO Asynchronous Falling Edge Detect Enable Registers (GPAFENn) SYNOPSIS The asynchronous falling edge detect enable registers define the pins for which a asynchronous falling edge transition sets a bit in the event detect status registers (GPEDSn). Asynchronous means the incoming signal is not sampled by the system clock. As such falling edges of very short duration can be detected. Bit(s) Field Name 31-0 AFENn (n=0..31) Description 0 = Asynchronous falling edge detect disabled on GPIO pin n. 1 = Asynchronous falling edge on GPIO pin n sets corresponding bit in EDSn. Type Reset R/W 0 Table 6-26 GPIO Asynchronous Falling Edge Detect Status Register 0 Bit(s) Field Name 31-22 21-0 - Description Reserved pin n. 1 = Asynchronous falling edge on GPIO pin n sets corresponding bit in EDSn. Type Reset R R/W 0 0 AFENn (n=32..53) 0 = Asynchronous fa...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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