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Unformatted text preview: e increment to apply to the destination address at the end of each row in 2D mode. Source Stride (2D Mode) Signed (2 s complement) byte increment to apply to the source address at the end of each row in 2D mode. Type Reset RW 0x0 Field Name D_STRIDE 15:0 S_STRIDE RW 0x0 0_NEXTCONBK 1_NEXTCONBK 2_NEXTCONBK 3_NEXTCONBK 4_NEXTCONBK 5_NEXTCONBK 6_NEXTCONBK 7_NEXTCONBK 8_NEXTCONBK 9_NEXTCONBK 10_NEXTCONBK 11_NEXTCONBK 12_NEXTCONBK 13_NEXTCONBK 14_NEXTCONBK Register
Synopsis DMA Next Control Block Address The value loaded into this register can be overwritten so that the linked list of Control Block data structures can be altered. However it is only safe to do this when the DMA is paused. The address must be 256 bit aligned and so the bottom 5 bits cannot be set and will read back as zero. Description Address of next CB for chained DMA operations. Type Reset RW 0x0 Bit(s) Field Name 31:0 ADDR 0_DEBUG 1_DEBUG 2_DEBUG 3_DEBUG 4_DEBUG 5_DEBUG 6_DEBUG Register
Synopsis Bit(s) 31:29 DMA Debug register. Description Reserved - Write as 0, read as don't care Type Reset Field Name 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 54 28 LITE DMA Lite Set if the DMA is a reduced performance LITE engine. DMA Version DMA version number, indicating control bit filed changes. DMA State Machine State Returns the value of the DMA engines state machine for this channel. DMA ID Returns the DMA AXI ID of this DMA channel. DMA Outstanding Writes Counter Returns the number of write responses that have not yet been received. This count is reset at the start of each new DMA transfer or with a DMA reset. Reserved - Write as 0, read as don't care RO 0x0 27:25 VERSION RO 0x2 24:16 DMA_STATE RO 0x0 15:8 DMA_ID RO 0x0 7:4 OUTSTANDING_WRITES RO 0x0 3 2 READ_ERROR Slave Read Response Error Set if the read operation returned an error value on the read response bus. It can be cleared by writing a 1, Fifo Error Set if the optional read Fifo records an error condition. It can be cleared by writing a 1, Read Last Not Set Error If the AXI read last signal was not set when expected, then this error bit will be set. It can be cleared by writing a 1. RW 0x0 1 FIFO_ERROR RW 0x0 0 READ_LAST_NOT_SET_ERROR RW 0x0 7_TI 8_TI 9_TI 10_TI 11_TI 12_TI 13_TI 14_TI Register
Synopsis Bit(s) 31:26 DMA Transfer Information. Description Reserved - Write as 0, read as don't care Type Reset Field Name 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 55 25:21 WAITS Add Wait Cycles This slows down the DMA throughput by setting the number of dummy cycles burnt after each DMA read or write operation is completed. A value of 0 means that no wait cycles are to be added. Peripheral Mapping Indicates the peripheral number (1-31) whose ready signal shall be used to control the rate of the transfers, and whose panic signals will be output on the DMA AXI bus. Set to 0 for a continuous un-paced transfer. Burst Transfer Length Indicates the burst length of the DMA transfers. The DMA will attempt to transfer data as bursts of this number of words. A value of zero will produce a single transfer. Bursts are only produced for specific conditions, see main text. RW 0x0 20:16 PERMAP RW 0x0 15:12 BURST_LENGTH RW 0x0 11 10 SRC_IGNORE SRC_DREQ Control Source Reads with DREQ 1 = The DREQ selected by PER_MAP will gate the source reads. 0 = DREQ has no effect. Source Transfer Width 1 = Use 128-bit source read width. 0 = Use 32-bit source read width. Source Address Increment 1 = Source address increments after each read. The address will increment by 4, if S_WIDTH=0 else by 32. 0 = Source address does not change. RW RW 0x0 0x0 9 SRC_WIDTH RW 0x0 8 SRC_INC RW 0x0 7 6 DEST_IGNORE DEST_DREQ Control Destination Writes with DREQ 1 = The DREQ selected by PERMAP will gate the destination writes. 0 = DREQ has no effect. Destination Transfer Width 1 = Use 128-bit destination write width. 0 = Use 32-bit destination write width. RW RW 0x0 0x0 5 DEST_WIDTH RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 56 4 DEST_INC Destination Address Increment 1 = Destination address increments after each write The address will increment by 4, if DEST_WIDTH=0 else by 32. 0 = Destination address does not change. Wait for a Write Response When set this makes the DMA wait until it receives the AXI write response for each write. This ensures that multiple writes cannot get stacked in the AXI bus pipeline. 1= Wait for the write response to be received before proceeding. 0 = Don t wait; continue as soon as the write data is sent. Reserved - Write as 0, read as don't care RW 0x0 3 WAIT_RESP RW 0x0 2:1 0 INTEN Interrupt Enable 1 = Generate an interrupt when the transfer described by the current Control Block completes. 0 = Do not generate an interrupt. RW 0x0 7_TXFR_LEN...
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- Spring '13