Broadcom BCM2835

The module does not check for any framing errors

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Unformatted text preview: ts for one half bit time and then starts scanning for the next start bit. The mini UART does not check if the stop bit is high or wait for the stop bit to appear. As a result of this a UART1_RX input line which is continuously low (a break condition or an error in connection or GPIO setup) causes the receiver to continuously receive 0x00 symbols. The mini UART uses 8-times oversampling. The Baudrate can be calculated from: system _ clock _ freq baudrate = 8 * (baudrate _ reg + 1) If the system clock is 250 MHz and the baud register is zero the baudrate is 31.25 Mega baud. (25 Mbits/sec or 3.125 Mbytes/sec). The lowest baudrate with a 250 MHz system clock is 476 Baud. When writing to the data register only the LS 8 bits are taken. All other bits are ignored. When reading from the data register only the LS 8 bits are valid. All other bits are zero. 2.2.2 Mini UART register details. AUX_MU_IO_REG Register (0x7E21 5040) SYNOPSIS The AUX_MU_IO_REG register is primary used to write data to and read data from the UART FIFOs. If the DLAB bit in the line control register is set this register gives access to the LS 8 bits of the baud rate. (Note: there is easier access to the baud rate register) Bit(s) 31:8 7:0 Field Name Description Reserved, write zero, read as don't care Type Reset LS 8 bits Baudrate read/write, DLAB=1 Transmit data write, DLAB=0 Receive data read, DLAB=0 Access to the LS 8 bits of the 16-bit baudrate register. (Only If bit 7 of the line control register (DLAB bit) is set) Data written is put in the transmit FIFO (Provided it is not full) (Only If bit 7 of the line control register (DLAB bit) is clear) Data read is taken from the receive FIFO (Provided it is not empty) (Only If bit 7 of the line control register (DLAB bit) is clear) R/W 0 7:0 W 0 7:0 R 0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 11 AUX_MU_IIR_REG Register (0x7E21 5044) SYNOPSIS The AUX_MU_IER_REG register is primary used to enable interrupts If the DLAB bit in the line control register is set this register gives access to the MS 8 bits of the baud rate. (Note: there is easier access to the baud rate register) Bit(s) 31:8 7:0 Field Name Description Reserved, write zero, read as don't care Type Reset MS 8 bits Baudrate read/write, DLAB=1 Access to the MS 8 bits of the 16-bit baudrate register. R/w (Only If bit 7 of the line control register (DLAB bit) is set) Reserved, write zero, read as don't care Some of these bits have functions in a 16550 compatible UART but are ignored here 0 7:2 1 Enable receive If this bit is set the interrupt line is asserted whenever interrupt the receive FIFO holds at least 1 byte. (DLAB=0) If this bit is clear no receive interrupts are generated. Enable transmit interrupt (DLAB=0) R 0 0 If this bit is set the interrupt line is asserted whenever R the transmit FIFO is empty. If this bit is clear no transmit interrupts are generated. 0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 12 AUX_MU_IER_REG Register (0x7E21 5048) SYNOPSIS The AUX_MU_IIR_REG register shows the interrupt status. It also has two FIFO enable status bits and (when writing) FIFO clear bits. Bit(s) 31:8 7:6 5:4 3 2:1 Field Name Description Reserved, write zero, read as don't care Type Reset FIFO enables - Both bits always read as 1 as the FIFOs are always enabled Always read as zero Always read as zero as the mini UART has no timeout function R R R R/W 11 00 0 00 READ: On read this register shows the interrupt ID bit Interrupt ID 00 : No interrupts bits 01 : Transmit holding register empty WRITE: 10 : Receiver holds valid byte FIFO clear 11 : <Not possible> bits On write: Writing with bit 1 set will clear the receive FIFO Writing with bit 2 set will clear the transmit FIFO Interrupt pending This bit is clear whenever an interrupt is pending 0 R 1 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 13 AUX_MU_LCR_REG Register (0x7E21 504C) SYNOPSIS The AUX_MU_LCR_REG register controls the line data format and gives access to the baudrate register Bit(s) 31:8 7 Field Name Description Reserved, write zero, read as don't care Type Reset DLAB access If set the first to Mini UART register give access the the Baudrate register. During operation this bit must be cleared. R/W 0 6 Break If set high the UART1_TX line is pulled low R/W continuously. If held for at least 12 bits times that will indicate a break condition. Reserved, write zero, read as don't care Some of these bits have functions in a 16550 compatible UART but are ignored here 0 5:1 0 data size 0 R/W 0 If clear the UART works in 7-bit mode If set the UART works in 8-bit mode AUX_MU_MCR_REG Register (0x7E21 5050) SYNOPSIS The AUX_MU_MCR_REG register controls the 'modem' signals. Bit(s) 31:8 7:2 1 Field Name Description Reserved, write zero, read as don't care Reserved, write zero, read as don't care Some of these bits have functions in a 16550 compatible U...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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