Broadcom BCM2835

The other registers ti sourcead destad txfrlen stride

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Unformatted text preview: responding bit locations in the CB data structure in memory. 32-bit Word Offset 0 1 2 3 4 5 6-7 Associated Read-Only Register TI SOURCE_AD DEST_AD TXFR_LEN STRIDE NEXTCONBK N/A Description Transfer Information Source Address Destination Address Transfer Length 2D Mode Stride Next Control Block Address Reserved set to zero. Table 4-2 DMA Control Block Definition The DMA is started by writing the address of a CB structure into the CONBLK_AD register and then setting the ACTIVE bit. The DMA will fetch the CB from the address set in the SCB_ADDR field of this reg and it will load it into the read-only registers described below. It will then begin a DMA transfer according to the information in the CB. When it has completed the current DMA transfer (length => 0) the DMA will update the CONBLK_AD register with the contents of the NEXTCONBK register, fetch a new CB from that address, and start the whole procedure once again. The DMA will stop (and clear the ACTIVE bit) when it has completed a DMA transfer and the NEXTCONBK register is set to 0x0000_0000. It will load this value into the CONBLK_AD reg and then stop. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 40 Most of the control block registers cannot be written to directly as they loaded automatically from memory. They can be read to provide status information, and to indicate the progress of the current DMA transfer. The value loaded into the NEXTCONBK register can be overwritten so that the linked list of Control Block data structures can be dynamically altered. However it is only safe to do this when the DMA is paused. 4.2.1.2 Register Map DMA Address Map Address Offset 0x0 0x4 0x8 0xc 0x10 0x14 0x18 0x1c 0x20 0x100 0x104 0x108 0x10c 0x110 0x114 Register Name Description Size 0_CS 0_CONBLK_AD 0_TI 0_SOURCE_AD 0_DEST_AD 0_TXFR_LEN 0_STRIDE 0_NEXTCONBK 0_DEBUG 1_CS 1_CONBLK_AD 1_TI 1_SOURCE_AD 1_DEST_AD 1_TXFR_LEN DMA Channel 0 Control and Status DMA Channel 0 Control Block Address DMA Channel 0 CB Word 0 (Transfer Information) DMA Channel 0 CB Word 1 (Source Address) DMA Channel 0 CB Word 2 (Destination Address) DMA Channel 0 CB Word 3 (Transfer Length) DMA Channel 0 CB Word 4 (2D Stride) DMA Channel 0 CB Word 5 (Next CB Address) DMA Channel 0 Debug DMA Channel 1 Control and Status DMA Channel 1 Control Block Address DMA Channel 1 CB Word 0 (Transfer Information) DMA Channel 1 CB Word 1 (Source Address) DMA Channel 1 CB Word 2 (Destination Address) DMA Channel 1 CB Word 3 (Transfer Length) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 41 0x118 0x11c 0x120 0x200 0x204 0x208 0x20c 0x210 0x214 0x218 0x21c 0x220 0x300 0x304 0x308 0x30c 0x310 0x314 0x318 0x31c 0x320 1_STRIDE 1_NEXTCONBK 1_DEBUG 2_CS 2_CONBLK_AD 2_TI 2_SOURCE_AD 2_DEST_AD 2_TXFR_LEN 2_STRIDE 2_NEXTCONBK 2_DEBUG 3_CS 3_CONBLK_AD 3_TI 3_SOURCE_AD 3_DEST_AD 3_TXFR_LEN 3_STRIDE 3_NEXTCONBK 3_DEBUG DMA Channel 1 CB Word 4 (2D Stride) DMA Channel 1 CB Word 5 (Next CB Address) DMA Channel 1 Debug DMA Channel 2 Control and Status DMA Channel 2 Control Block Address DMA Channel 2 CB Word 0 (Transfer Information) DMA Channel 2 CB Word 1 (Source Address) DMA Channel 2 CB Word 2 (Destination Address) DMA Channel 2 CB Word 3 (Transfer Length) DMA Channel 2 CB Word 4 (2D Stride) DMA Channel 2 CB Word 5 (Next CB Address) DMA Channel 2 Debug DMA Channel 3 Control and Status DMA Channel 3 Control Block Address DMA Channel 3 CB Word 0 (Transfer Information) DMA Channel 3 CB Word 1 (Source Address) DMA Channel 3 CB Word 2 (Destination Address) DMA Channel 3 CB Word 3 (Transfer Length) DMA Channel 3 CB Word 4 (2D Stride) DMA Channel 3 CB Word 5 (Next CB Address) DMA Channel 0 Debug 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 42 0x400 0x404 0x408 0x40c 0x410 0x414 0x418 0x41c 0x420 0x500 0x504 0x508 0x50c 0x510 0x514 0x518 0x51c 0x520 0x600 0x604 0x608 4_CS 4_CONBLK_AD 4_TI 4_SOURCE_AD 4_DEST_AD 4_TXFR_LEN 4_STRIDE 4_NEXTCONBK 4_DEBUG 5_CS 5_CONBLK_AD 5_TI 5_SOURCE_AD 5_DEST_AD 5_TXFR_LEN 5_STRIDE 5_NEXTCONBK 5_DEBUG 6_CS 6_CONBLK_AD 6_TI DMA Channel 4 Control and Status DMA Channel 4 Control Block Address DMA Channel 4 CB Word 0 (Transfer Information) DMA Channel 4 CB Word 1 (Source Address) DMA Channel 4 CB Word 2 (Destination Address) DMA Channel 4 CB Word 3 (Transfer Length) DMA Channel 4 CB Word 4 (2D Stride) DMA Channel 4 CB Word 5 (Next CB Address) DMA Channel 0 Debug DMA Channel 5 Control and Status DMA Channel 5 Control Block Address DMA Channel 5 CB Word 0 (Transfer Information) DMA Channel 5 CB Word 1 (Source Address) DMA Channel 5 CB Word 2 (Destination Address) DMA Channel 5 CB Word 3 (Transfer Length) DMA Channel 5 CB Word 4 (2D Stride) DMA Channel 5 CB Word 5 (Next CB Address) DMA Channel 5 Debug DMA Channel 6 Control and Status DMA Channel 6 Control Block Address DMA Channel 6 CB Word 0 (Transfer Information) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 43 0x60c 0x610 0x614 0x618 0x61c 0x620 0x700 0x704 0x708 0x70c 0x710 0x714 0x71c 0x720 0x800 0x804 0x808...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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