Broadcom BCM2835

The read only txd field is set when the fifo has

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Unformatted text preview: ata before reading. Reading from an empty FIFO will return invalid data. The read-only TXE field is set when the FIFO is empty. No further data will be transmitted until more data is written to the FIFO. The read-only RXF field is set when the FIFO is full. No more clocks will be generated until space is available in the FIFO to receive more data. The ERR field is set when the slave fails to acknowledge either its address or a data byte written to it. The ERR field is reset by writing a 1 , writing a 0 to the field has no effect. The CLKT field is set when the slave holds the SCL signal high for too long (clock stretching). The CLKT field is reset by writing a 1 , writing a 0 to the field has no effect. Description Reserved - Write as 0, read as don't care Type Reset Bit(s) 31:10 9 Field Name CLKT CLKT Clock Stretch Timeout 0 = No errors detected. 1 = Slave has held the SCL signal low (clock stretching) for longer and that specified in the I2CCLKT register Cleared by writing 1 to the field. ERR ACK Error 0 = No errors detected. 1 = Slave has not acknowledged its address. Cleared by writing 1 to the field. RXF - FIFO Full 0 = FIFO is not full. 1 = FIFO is full. If a read is underway, no further serial data will be received until data is read from FIFO. RW 0x0 8 ERR RW 0x0 7 RXF RO 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 31 6 TXE TXE - FIFO Empty 0 = FIFO is not empty. 1 = FIFO is empty. If a write is underway, no further serial data can be transmitted until data is written to the FIFO. RXD - FIFO contains Data 0 = FIFO is empty. 1 = FIFO contains at least 1 byte. Cleared by reading sufficient data from FIFO. TXD - FIFO can accept Data 0 = FIFO is full. The FIFO cannot accept more data. 1 = FIFO has space for at least 1 byte. RXR - FIFO needs Reading ( full) 0 = FIFO is less than full and a read is underway. 1 = FIFO is or more full and a read is underway. Cleared by reading sufficient data from the FIFO. TXW - FIFO needs Writing ( full) 0 = FIFO is at least full and a write is underway (or sufficient data to send). 1 = FIFO is less then full and a write is underway. Cleared by writing sufficient data to the FIFO. DONE Transfer Done 0 = Transfer not completed. 1 = Transfer complete. Cleared by writing 1 to the field. TA Transfer Active 0 = Transfer not active. 1 = Transfer active. RO 0x1 5 RXD RO 0x0 4 TXD RO 0x1 3 RXR RO 0x0 2 TXW RO 0x0 1 DONE RW 0x0 0 TA RO 0x0 DLEN Register Synopsis The data length register defines the number of bytes of data to transmit or receive in the I2C transfer. Reading the register gives the number of bytes remaining in the current transfer. The DLEN field specifies the number of bytes to be transmitted/received. Reading the DLEN field when a transfer is in progress (TA = 1) returns the number of bytes still to be transmitted or received. Reading the DLEN field when the transfer has just completed (DONE = 1) returns zero as there are no more bytes to transmit or receive. Finally, reading the DLEN field when TA = 0 and DONE = 0 returns the last value written. The DLEN field can be left over multiple transfers. Description Reserved - Write as 0, read as don't care Type Reset Bit(s) 31:16 Field Name 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 32 15:0 DLEN Data Length. Writing to DLEN specifies the number of bytes to be transmitted/received. Reading from DLEN when TA = 1 or DONE = 1, returns the number of bytes still to be transmitted or received. Reading from DLEN when TA = 0 and DONE = 0, returns the last DLEN value written. DLEN can be left over multiple packets. RW 0x0 A Register Synopsis The slave address register specifies the slave address and cycle type. The address register can be left across multiple transfers The ADDR field specifies the slave address of the I2C device. Description Reserved - Write as 0, read as don't care ADDR Slave Address. RW 0x0 Type Reset Bit(s) 31:7 6:0 Field Name FIFO Register Synopsis The Data FIFO register is used to access the FIFO. Write cycles to this address place data in the 16-byte FIFO, ready to transmit on the BSC bus. Read cycles access data received from the bus. Data writes to a full FIFO will be ignored and data reads from an empty FIFO will result in invalid data. The FIFO can be cleared using the I2CC.CLEAR field. The DATA field specifies the data to be transmitted or received. Description Reserved - Write as 0, read as don't care DATA Writes to the register write transmit data to the FIFO. Reads from register reads received data from the FIFO. RW 0x0 Type Reset Bit(s) 31:8 7:0 Field Name DIV Register 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 33 Synopsis The clock divider register is used to define the clock speed of the BSC peripheral. The CDIV field specifies the core clock...
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