Broadcom BCM2835

Broadcom BCM2835

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Unformatted text preview: ne (the last one still being received). Note that there is no "receive FIFO full" interrupt or "receive FIFO overflow" flag as the number of entries received can never be more then the number of entries transmitted. AUX is IDLE: This interrupt will be asserted when the module has finished all activities, including waiting the minimum CS high time. This guarantees that any receive data will be available and `transparent' changes can be made to the configuration register (e.g. inverting the SPI clock polarity). AUXSPI0/1_STAT Register (0x7E21 5088,0x7E21 50C8) SYNOPSIS The AUXSPIx_STAT registers show the status of the SPI interfaces. Bit(s) Field Name Description 31:24 TX FIFO level The number of data units in the transmit data FIFO 23:12 RX FIFO level The number of data units in the receive data FIFO. 11:5 4 3 2 6 5:0 TX Full TX Empty RX Empty Busy Bit count Reserved, write zero, read as don't care If 1 the transmit FIFO is full If 0 the transmit FIFO can accept at least 1 data unit. If 1 the transmit FIFO is empty If 0 the transmit FIFO holds at least 1 data unit. If 1 the receiver FIFO is empty If 0 the receiver FIFO holds at least 1 data unit. Indicates the module is busy transferring data. The number of bits still to be processed. Starts with 'shift-length' and counts down. Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 25 Busy This status bit indicates if the module is busy. It will be clear when the TX FIFO is empty and the module has finished all activities, including waiting the minimum CS high time. AUXSPI0/1_PEEK Register (0x7E21 508C,0x7E21 50CC) SYNOPSIS The AUXSPIx_PEEK registers show received data of the SPI interfaces. Bit(s) Field Name 31:16 15:0 Data Description Reserved, write zero, read as don't care Type Reset Reads from this address will show the top entry from RO the receive FIFO, but the data is not taken from the FIFO. This provides a means of inspecting the data but not removing it from the FIFO. 0 AUXSPI0/1_IO Register (0x7E21 50A0-0x7E21 50AC 0x7E21 50E0-0x7E21 50EC) SYNOPSIS The AUXSPIx_IO registers are the primary data port of the SPI interfaces These four addresses all write to the same FIFO. Writing to any of these addresses causes the SPI CS_n pins to be de-asserted at the end of the access Bit(s) Field Name 31:16 15:0 Data Description Reserved, write zero, read as don't care Type Reset Writes to this address range end up in the transmit R/W 0 FIFO. Data is lost when writing whilst the transmit FIFO is full. Reads from this address will take the top entry from the receive FIFO. Reading whilst the receive FIFO is will return the last data received. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 26 AUXSPI0/1_TXHOLD Register (0x7E21 50B0-0x7E21 50BC 0x7E21 50F0-0x7E21 50FC) SYNOPSIS The AUXSPIx_TXHOLD registers are the extended CS port of the SPI interfaces These four addresses all write to the same FIFO. Writing to these addresses causes the SPI CS_n pins to remain asserted at the end of the access Bit(s) Field Name 31:16 15:0 Data Description Reserved, write zero, read as don't care Type Reset Writes to this address range end up in the transmit R/W 0 FIFO. Data is lost when writing whilst the transmit FIFO is full. Reads from this address will take the top entry from the receive FIFO. Reading whilst the receive FIFO is will return the last data received. 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 27 3 BSC 3.1 Introduction The Broadcom Serial Controller (BSC) controller is a master, fast-mode (400Kb/s) BSC controller. The Broadcom Serial Control bus is a proprietary bus compliant with the Philips I2C bus/interface version 2.1 January 2000. I2C single master only operation (supports clock stretching wait states) Both 7-bit and 10-bit addressing is supported. Timing completely software controllable via registers 3.2 Register View The BSC controller has eight memory-mapped registers. All accesses are assumed to be 32bit. Note that the BSC2 master is used dedicated with the HDMI interface and should not be accessed by user programs. There are three BSC masters inside BCM. The register addresses starts from BSC0: 0x7E20_5000 BSC1: 0x7E80_4000 BSC2 : 0x7E80_5000 The table below shows the address of I2C interface where the address is an offset from one of the three base addreses listed above. I2C Address Map Address Offset 0x0 0x4 0x8 0xc 0x10 0x14 0x18 Register Name Description Control Status Data Length Slave Address Data FIFO Clock Divider Data Delay Size 32 32 32 32 32 32 32 C S DLEN A FIFO DIV DEL 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 28 0x1c CLKT Clock Stretch Timeout 32 C Regist...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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