Broadcom BCM2835

This bit is cleared to 0 on reset to disable loopback

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Unformatted text preview: s don't care Overrun error interrupt mask. A read returns the current mask for the interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. RW 0x0 Type Reset 9 BEIM Break error interrupt mask. A read returns RW the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the interrupt is set. A write of 0 clears the mask. Parity error interrupt mask. A read returns RW the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the interrupt is set. A write of 0 clears the mask. Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the interrupt is set. A write of 0 clears the mask. RW 0x0 8 PEIM 0x0 7 FEIM 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 188 6 RTIM Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the interrupt is set. A write of 0 clears the mask. RW 0x0 5 TXIM Transmit interrupt mask. A read returns the RW current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the interrupt is set. A write of 0 clears the mask. Receive interrupt mask. A read returns the RW current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the interrupt is set. A write of 0 clears the mask. Unsupported, write zero, read as don't care Unsupported, write zero, read as don't care nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the interrupt is set. A write of 0 clears the mask. Unsupported, write zero, read as don't care RO RO RW 0x0 4 RXIM 0x0 3 2 1 DSRMIM DCDMIM CTSMIM 0x0 0x0 0x0 0 RIMIM RO 0x0 RIS Register Synopsis The UART_RIS Register is the raw interrupt status register. It is a read-only register. This register returns the current raw status value, prior to masking, of the corresponding interrupt. NOTE: All the bits, except for the modem status interrupt bits (bits 3 to 0), are cleared to 0 when reset. The modem status interrupt bits are undefined after reset. Bit(s) Field Name 31:11 Description Reserved - Write as 0, read as don't care Type Reset 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 189 10 OERIS Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. Unsupported, write zero, read as don't care Unsupported, write zero, read as don't care nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. Unsupported, write zero, read as don't care RW 0x0 9 BERIS RW 0x0 8 PERIS RW 0x0 7 FERIS RW 0x0 6 RTRIS RW 0x0 5 TXRIS RW 0x0 4 RXRIS RW 0x0 3 2 1 DSRRMIS DCDRMIS CTSRMIS RW RW RW 0x0 0x0 0x0 0 RIRMIS RW 0x0 MIS Register 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 190 Synopsis The UART_MIS Register is the masked interrupt status register. This register returns the current masked status value of the corresponding interrupt. NOTE: All the bits, except for the modem status interrupt bits (bits 3 to 0), are cleared to 0 when reset. The modem status interrupt bits are undefined after reset. Bit(s) Field Name 31:11 10 OEMIS Description Reserved - Write as 0, read as don't care Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. Unsupported, write zero, read as don't care Unsupported, write zero, read as don't care nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. Unsupported, write zero, read as don't care RW 0x0 Type Reset 9 BEMIS RW...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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