Broadcom BCM2835

This compensates the dma latency when writing data to

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Unformatted text preview: card. It determines by how many steps the sampling clock is delayed in SDR mode. Description Reserved - Write as 0, read as don't care STEPS Number of steps (0 to 40) RW 0x0 Type Reset Bit(s) 31:6 5:0 Field Name TUNE_STEPS_DDR Register 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 86 Synopsis This register is used to delay the card clock when sampling the returning data and command response from the card. It determines by how many steps the sampling clock is delayed in DDR mode. Description Reserved - Write as 0, read as don't care Type Reset Bit(s) 31:6 5:0 Field Name STEPS Number of steps (0 to 40) RW 0x0 SPI_INT_SPT Register Synopsis This register controls whether assertion of interrupts in SPI mode is possible independent of the card select line. For the exact details please refer to the Arasan documentation SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf. Bit marked as reserved in this document but not by the Arasan documentation refer to functionality which has been disabled due to the changes listed in the previous chapter. Description Reserved - Write as 0, read as don't care SELECT Interrupt independent of card select line: 0 = no 1 = yes RW 0x0 Type Reset Bit(s) 31:8 7:0 Field Name SLOTISR_VER Register Synopsis This register contains the version information and slot interrupt status. For the exact details please refer to the Arasan documentation SD3.0_Host_AHB_eMMC4.4_Usersguide_ver5.9_jan11_10.pdf. Bit marked as reserved in this document but not by the Arasan documentation refer to functionality which has been disabled due to the changes listed in the previous chapter. Description Vendor Version Number Host Controller specification version Type RW RW Reset 0x0 0x0 Bit(s) 31:24 23:16 Field Name VENDOR SDVERSION 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 87 15:8 7:0 SLOT_STATUS Reserved - Write as 0, read as don't care Logical OR of interrupt and wakeup signal for each slot RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 88 6 General Purpose I/O (GPIO) There are 54 general-purpose I/O (GPIO) lines split into two banks. All GPIO pins have at least two alternative functions within BCM. The alternate functions are usually peripheral IO and a single peripheral may appear in each bank to allow flexibility on the choice of IO voltage. Details of alternative functions are given in section 6.2. Alternative Function Assignments. The block diagram for an individual GPIO pin is given below : Figure 6-1 GPIO Block Diagram 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 89 The GPIO peripheral has three dedicated interrupt lines. These lines are triggered by the setting of bits in the event detect status register. Each bank has its' own interrupt line with the third line shared between all bits. The Alternate function table also has the pull state (pull-up/pull-down) which is applied after a power down. 6.1 Register View The GPIO has 41 registers. All accesses are assumed to be 32-bit. Read/ Write R/W R/W R/W R/W R/W R/W R/W W W W W R R R/W R/W R/W R/W R/W R/W Page 90 Address 0x 7E20 0000 0x 7E20 0000 0x 7E20 0004 0x 7E20 0008 0x 7E20 000C 0x 7E20 0010 0x 7E20 0014 0x 7E20 0018 0x 7E20 001C 0x 7E20 0020 0x 7E20 0024 0x 7E20 0028 0x 7E20 002C 0x 7E20 0030 0x 7E20 0034 0x 7E20 0038 0x 7E20 003C 0x 7E20 0040 0x 7E20 0044 0x 7E20 0048 0x 7E20 004C 0x 7E20 0050 0x 7E20 0054 0x 7E20 0058 0x 7E20 005C Field Name GPFSEL0 GPFSEL0 GPFSEL1 GPFSEL2 GPFSEL3 GPFSEL4 GPFSEL5 GPSET0 GPSET1 GPCLR0 GPCLR1 GPLEV0 GPLEV1 GPEDS0 GPEDS1 GPREN0 GPREN1 GPFEN0 GPFEN1 Description GPIO Function Select 0 GPIO Function Select 0 GPIO Function Select 1 GPIO Function Select 2 GPIO Function Select 3 GPIO Function Select 4 GPIO Function Select 5 Reserved GPIO Pin Output Set 0 GPIO Pin Output Set 1 Reserved GPIO Pin Output Clear 0 GPIO Pin Output Clear 1 Reserved GPIO Pin Level 0 GPIO Pin Level 1 Reserved GPIO Pin Event Detect Status 0 GPIO Pin Event Detect Status 1 Reserved GPIO Pin Rising Edge Detect Enable 0 GPIO Pin Rising Edge Detect Enable 1 Reserved GPIO Pin Falling Edge Detect Enable 0 GPIO Pin Falling Edge Detect Enable 1 Size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Address 0x 7E20 0060 0x 7E20 0064 0x 7E20 0068 0x 7E20 006C 0x 7E20 0070 0x 7E20 0074 0x 7E20 0078 0x 7E20 007C 0x 7E20 0080 0x 7E20 0084 0x 7E20 0088 0x 7E20 008C 0x 7E20 0090 0x 7E20 0094 0x 7E20 0098 0x 7E20 009C 0x 7E20 00A0 0x 7E20 00B0 Field Name GPHEN0 GPHEN1 GPLEN0 GPLEN1 GPAREN0 GPAREN1 GPAFEN0 GPAFEN1 GPPUD GPPUDCLK0 GPPUDCLK1 Reserved Description Size 32 32 32 32 32 32 32 32 32 32 32 4 Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W GPIO Pin High Detect Enable 0 GPIO Pin High Detect Enable 1 Reserved GPIO Pin Low Detect Enable 0 GPIO Pin Low Detect Enable 1 Reserved GPIO Pin Async. Rising Edge Detect 0 GPIO Pin Async. Rising Edge Detect 1 Reserved GPIO Pin Async. Falling Edge Detect 0 GPIO Pin Async. Falling Edge Detect 1 Reserved GPIO Pin Pull-up/down Enable GPIO Pin Pull-up/down Enable Clock 0 GPIO Pin Pull-up/down Enable...
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