Broadcom BCM2835

To send value nm within a periodic sequence of m

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Unformatted text preview: is the range. This mode may be preferred if high frequency modulation is not required or has negative effects. Channel sends its output continuously as long as data register is used, or buffer is used and it is not empty. Serial bit transmission when M/S Mode enabled Serialiser mode: Each channel is also capable of working as a serialiser. In this mode data written in buffer or the data register is sent serially. 9.5 Quick Reference PWM DMA is mapped to DMA channel 5. GPIOs are assigned to PWM channels as below. Please refer to GPIO section for further details: PWM0 GPIO 12 GPIO 13 GPIO 18 GPIO 19 GPIO 40 GPIO 41 GPIO 45 GPIO 52 GPIO 53 Alt Fun 0 Alt Fun 5 Alt Fun 0 Alt Fun 1 PWM1 Alt Fun 0 Alt Fun 5 Alt Fun 0 Alt Fun 0 Alt Fun 1 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 140 PWM clock source and frequency is controlled in CPRMAN. 9.6 Control and Status Registers PWM Address Map Address Offset 0x0 0x4 0x8 0x10 0x14 0x18 0x20 0x24 Register Name CTL STA DMAC RNG1 DAT1 FIF1 RNG2 DAT2 Description PWM Control PWM Status PWM DMA Configuration PWM Channel 1 Range PWM Channel 1 Data PWM FIFO Input PWM Channel 2 Range PWM Channel 2 Data Size 32 32 32 32 32 32 32 32 CTL Register 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 141 Synopsis PWENi is used to enable/disable the corresponding channel. Setting this bit to 1 enables the channel and transmitter state machine. All registers and FIFO is writable without setting this bit. MODEi bit is used to determine mode of operation. Setting this bit to 0 enables PWM mode. In this mode data stored in either PWM_DATi or FIFO is transmitted by pulse width modulation within the range defined by PWM_RNGi. When this mode is used MSENi defines whether to use PWM algorithm. Setting MODEi to 1 enables serial mode, in which data stored in either PWM_DATi or FIFO is transmitted serially within the range defined by PWM_RNGi. Data is transmitted MSB first and truncated or zeropadded depending on PWM_RNGi. Default mode is PWM. RPTLi is used to enable/disable repeating of the last data available in the FIFO just before it empties. When this bit is 1 and FIFO is used, the last available data in the FIFO is repeatedly sent. This may be useful in PWM mode to avoid duty cycle gaps. If the FIFO is not used this bit does not have any effect. Default operation is do-notrepeat. SBITi defines the state of the output when no transmission takes place. It also defines the zero polarity for the zero padding in serialiser mode. This bit is padded between two consecutive transfers as well as tail of the data when PWM_RNGi is larger than bit depth of data being transferred. this bit is zero by default. POLAi is used to configure the polarity of the output bit. When set to high the final output is inverted. Default operation is no inversion. USEFi bit is used to enable/disable FIFO transfer. When this bit is high data stored in the FIFO is used for transmission. When it is low, data written to PWM_DATi is transferred. This bit is 0 as default. CLRF is used to clear the FIFO. Writing a 1 to this bit clears the FIFO. Writing 0 has no effect. This is a single shot operation and reading the bit always returns 0. MSENi is used to determine whether to use PWM algorithm or simple M/S ratio transmission. When this bit is high M/S transmission is used. This bit is zero as default. When MODEi is 1, this configuration bit has no effect. Description Reserved - Write as 0, read as don't care Type Reset Bit(s) 31:16 15 Field Name MSEN2 Channel 2 M/S Enable 0: PWM algorithm is used 1: M/S transmission is used. Reserved - Write as 0, read as don't care RW 0x0 14 13 USEF2 Channel 1 Use Fifo 0: Data register is transmitted 1: Fifo is used for transmission Channel 1 Polarity 0 : 0=low 1=high 1: 1=low 0=high Channel 1 Silence Bit Defines the state of the output when no transmission takes place RW 0x0 12 POLA2 RW 0x0 11 SBIT2 RW 0x0 06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW 2012 Broadcom Corporation. All rights reserved Page 142 10 RPTL2 Channel 1 Repeat Last Data 0: Transmission interrupts when FIFO is empty 1: Last data in FIFO is transmitted repetedly until FIFO is not empty Channel 1 Mode 0: PWM mode 1: Serialiser mode Channel 1 Enable 0: Channel is disabled 1: Channel is enabled Channel 1 M/S Enable 0: PWM algorithm is used 1: M/S transmission is used. Clear Fifo 1: Clears FIFO 0: Has no effect This is a single shot operation. This bit always reads 0 Channel 1 Use Fifo 0: Data register is transmitted 1: Fifo is used for transmission Channel 1 Polarity 0 : 0=low 1=high 1: 1=low 0=high Channel 1 Silence Bit Defines the state of the output when no transmission takes place Channel 1 Repeat Last Data 0: Transmission interrupts when FIFO is empty 1: Last data in FIFO is transmitted repetedly until FIFO is...
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This note was uploaded on 04/17/2013 for the course EEC 193 taught by Professor Kevin during the Spring '13 term at UC Davis.

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